Evaluating energy tradeoffs in coded systems

Turbo码和低密度奇偶校验(LDPC)码是操作非常接近通信信道的香农容量界限的两类前向差错控制码。在过去的十年里，人们对代码性能和译码硬件实现的各个方面进行了研究。硬件实现的研究集中在低功耗或高吞吐量的实现上，而代码设计的研究集中在开发在非常低的信噪比(SNR)下操作的代码。由于许多原因，错误控制系统的设计传统上将代码的设计与其相关译码硬件的设计分开。这种两步过程阻止了代码设计者在他们的设计模型和方法中考虑译码性能规范，如功耗。然而，我最近的一些研究结果表明，密度的演变，LDPC码设计中使用的技术之一，可以洞察解码器中的触发统计，从而了解解码器的动态功耗。因此，当评估几个码的信噪比性能时，人们可以使用类似的信息理论工具来评估解码器的功率权衡。该提案是在编码理论和微电子学的交叉点上，集中在这些最近的研究成果的扩展。该提案的长期目标是开发编码系统的设计和分析技术，这些技术在码设计过程中考虑到解码器的计算能量。这将需要研究能够分析解码器功耗的工具，可能基于但不限于密度演化技术，并将需要使用来自制造集成电路或基于现场可编程门阵列设计的物理测量来验证分析结果。

Turbo codes and low-density parity-check (LDPC) codes are two categories of forward error control codes that operate very close to the Shannon capacity bound for communication channels. During the past decade, various aspects of code performance and decoder hardware implementation have been investigated.  Hardware implementation research has focused on either low power or high throughput implementations, whereas code design research has focused on the development of codes that operate at very low signal-to-noise ratios (SNRs).For many reasons, the design of error control systems has traditionally separated the design of a code from the design of its associated decoder hardware.  This two-step process prevents code designers from accounting for decoder performance specifications, such as power consumption, in their design models and methodology.  However, some of my recent research results have demonstrated that density evolution, one of the techniques used in LDPC code design, can provide insight into the toggling statistics in a decoder, and hence into a decoder's dynamic power consumption.   Thus, when evaluating several codes for their SNR performance, one could additionally evaluate decoder power tradeoffs using similar information theoretic tools.This proposal, at the intersection of coding theory and microelectronics, focuses on an extension of these recent research results.  The long-term objectives of the proposal are to develop design and analysis techniques for coded systems that account for decoder computational energy in the code design process.  This will require research into tools that are capable of analyzing decoder power consumption, possibly based on but not limited to density evolution techniques, and will require the verification of analytical results using physical measurements from fabricated integrated circuits or field-programmable gate array-based designs.