Methods for improving the physical optimization of asics structured asics and fpgas

现代集成电路设计者面临着许多问题：（1）电路很大，需要可扩展的算法;（2）不同的设计风格，包括ASIC，结构化ASIC和FPGA;（3）设计有多个目标，包括线长，可布线性和时序。布局仍然是物理设计中的关键步骤;它消耗大量的运行时间，并在很大程度上决定了整体互连。近几年来，就业安置在研究活动中得到了复兴。 本提案旨在改进ASIC、结构化ASIC和FPGA设计风格的最新布局。

Many issues confront modern IC designers: (1) circuits are large and require scalable algorithms; (2) different design styles are available, including ASICs, structured ASICs, and FPGAs; (3) designs have multiple objectives including wire length, routability and timing. Placement remains a pivotal step in physical design; it consumes significant run-time and largely determines the overall interconnect. Placement has enjoyed a renaissance in research activity in recent years. The intent of this proposal to improve upon the state-of-the-art in placement for ASIC, structured ASIC, and FPGA design styles.