Next-generation programmable logic devices: improving silicon efficiency and designer productivity

在最新的制造技术中，一个晶体管的长度只有28纳米，一个计算机芯片可以容纳50亿个晶体管。这种令人难以置信的晶体管密度使前所未有的处理成为可能，但随之而来的是一个重大的经济挑战——设计和制造28纳米芯片的成本超过6000万美元。很少有市场大到足以证明定制的单一用途计算机芯片的成本是合理的，因此越来越多的芯片必须具有高度可编程性，以瞄准足够大的市场，从而在经济上可行。

In the latest manufacturing technology the length of a transistor is only 28 nm and 5 billion transistors will fit on a single computer chip. This incredible transistor density enables unprecedented processing, but comes with a major economic challenge -- it costs over $60M to design and manufacture a 28 nm chip. Few markets are large enough to justify the cost of a custom, single-purpose computer chip, so increasingly chips must be highly programmable to target a large enough market to be economically viable. One type of highly programmable chip is a Field Programmable Gate Array (FPGA). In FPGAs, a large number of programmable function blocks are connected by programmable routing. The processing performed by each function block can be changed by loading different "configuration bits", and the connections between blocks are made by programmable transistor-based switches, rather than fixed wires. Together these two forms of reprogrammability allow any circuit to be implemented in an FPGA, without the design and manufacture of a custom chip. FPGAs have become very important devices with sales of over $5 billion/year, and usage in diverse markets from high-end communications equipment to children's electronic games. FPGA reprogrammability comes at a cost; circuits in FPGAs are larger, slower and more power-hungry than those in a custom chip. This reserach seeks to make FPGAs more efficient for their key applications, such as wireless communication systems, by finding new FPGA function block that make them more efficient in these key domains. Another aspect of this research seeks methods by which FPGA power can be reduced to the point that they are suitable for use in battery-operated devices. Finally, to implement a design in an FPGA requires a sophicated Computer-Aided Design (CAD) tool which can transform an engineer's description of a circuit into the millions of programming bits that configure the FPGA to perform that function. As FPGA capacity increases it becomes more difficult for CAD tools to implement ever-larger designs efficiently and in a reasonable processing time; we seek to address this shortfall to keep FPGA designers productive.