Understanding the hardware-level requirements of deep learning algorithms

在每个计算设备的核心，都有一个或多个处理核心，它们操纵数据值并在存储设备或与物理世界交互的设备（如显示器、触摸屏和麦克风）之间移动它们。在过去的几十年里，核心性能，即数据值可以被操纵或移动的速度，每两年翻一番。这使得应用程序的复杂性和广度得以提高。然而，近年来，由于基础制造技术半导体的根本性转变，这种业绩趋势已经停止。提高数据中心和移动的平台中硬件设备性能的一个关键方向是硬件加速器。加速器是一种硬件，能够以更高的性能和能效执行特定应用所需的任务。专用加速器可以提供巨大的性能和能源效益 （100x-1000x）。 与此同时，基于机器学习的应用程序正在引领计算的新时代。不幸的是，这些应用程序对现有的硬件系统造成了压力，并且确实需要进一步的性能来发展。因此，所提出的研究的目标是了解机器学习算法的子集的计算和存储器通信要求。这项工作的结果将用于指导硬件的进一步研究和开发，以更好地满足机器学习应用的需求。

At the heart of every computing device, there are one or more processing cores that manipulate data values and move them among storage devices or devices that interact with the physical world such as displays, touch screens, and microphones. For the past several decades, core performance, that is the rate at which data values could be manipulated or moved around, has doubled every two years. This has enabled advances in application sophistication and breadth. However, in recent years, this performance trend has ceased as a result of fundamental shifts in semiconductors, the underlying manufacturing technology. One key direction to improve the performance of hardware devices in both data centers and mobile platforms is hardware accelerators. An accelerator is a piece of hardware able to perform the tasks required by a specific application with higher performance and energy efficiency. Specialized accelerators can offer large performance and energy benefits (100x-1000x). At the same time, machine-learning based applications are ushering a new era in computing. Unfortunately, these applications stress existing hardware systems and do require further performance to evolve. Accordingly the goal of the proposed research is to understand the compute and memory communication requirements of a subset of machine-learning algorithms. The results of this work will be used to steer further research and development in hardware to better suit the needs of machine-learning applications.