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SHF: Small: Hardware-Level Security to Side-Channel Analysis Attacks

SHF: Small: Hardware-Level Security to Side-Channel Analysis Attacks
SHF:小型:针对侧通道分析攻击的硬件级安全性
批准号:
1816069
负责人:
Marios Papaefthymiou
金额:
$45.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2018
资助国家:
美国
项目状态:
已结题
起止时间:
2018-10-01 至 2024-09-30

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中文摘要
翻译
计算机天生就容易受到所谓的侧信道安全攻击,这种攻击将其操作特性(例如,功耗)与存储在其中的秘密信息(例如,加密密钥)联系起来。先前旨在解决此漏洞的方法受到过高的功率、面积和性能开销的阻碍。本研究项目探索设计安全计算机的技术,使用有可能产生比传统计算硬件更安全的计算设备的技术,而在性能、面积和能源效率方面几乎没有牺牲。这项研究工作还包括为高级本科设计课程开发项目,并通过各种推广计划吸引高中生参与。该项目将探索新的硬件设计技术,这些技术固有地抵抗侧信道攻击,同时实现与主流设计技术相比有利的性能、面积和功率水平。具体来说,它将探索电路拓扑结构,回收用于其操作的能量,产生卓越的能源效率和平坦的功耗配置文件,不受侧信道攻击。它还将探索具有面积高效逻辑家族和可抵抗侧信道攻击的平坦功耗配置文件的管道架构。提出的技术将通过硅原型的设计、制造和实验评估进行评估。该奖项反映了美国国家科学基金会的法定使命,并通过使用基金会的知识价值和更广泛的影响审查标准进行评估,被认为值得支持。
英文摘要
Computers are inherently vulnerable to so-called side-channel security attacks that correlate their operating characteristics (e.g., power consumption) with secret information stored in them (e.g., cryptographic keys). Previous approaches aimed at addressing this vulnerability are hampered by prohibitively-high power, area, and performance overheads. This research project explores technologies for designing secure computers, using technologies that have the potential to yield computing devices that are significantly more secure than conventional computing hardware with little-or-no sacrifice in performance, area, and energy efficiency. This research effort also includes the development of projects for advanced undergraduate-level design courses, and the engagement of high-school students through a variety of outreach programs.This project will explore novel hardware design technologies that are inherently resistant to side-channel attacks while achieving performance, area, and power levels that compare favorably with mainstream design technologies. Specifically, it will explore circuit topologies that recycle the energy used for their operation, yielding superior energy efficiency and a flat power consumption profile that is immune to side-channel attacks. It will also explore pipeline architectures with area-efficient logic families and a flat power consumption profile that can resist side-channel attacks. The proposed technologies will be evaluated through the design, fabrication, and experimental evaluation of silicon prototypes.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
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FuSe-TG: Regaining the Edge
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