Design Automation Algorithms for High-Speed Integrated Circuits and Microsystems

集成电路技术的进步已经增加了电子设备的设计复杂性和操作信号速度，并且对电子设计自动化（EDA）工具提出了显著的要求以提供相同的效率和准确性。减小特征尺寸、增加封装密度和工作频率需要多学科的设计方法，如电气、热和电磁分析，以准确地模拟高速电路的信号和电源完整性。随着工作频率的提高，信号延迟、失真、串扰和衰减等信号完整性问题占主导地位，并显著降低电路性能。这些影响存在于整个设计过程中的芯片，封装，印刷电路板和背板的水平。一般来说，分布式电路使用偏微分方程建模，并且当离散化时产生大型方程系统，其求解在计算上是昂贵的。此外，由于集成电路封装密度的增加，对具有许多端口的高度耦合互连和配电网络进行建模变得至关重要。因此，传统EDA工具的底层算法在解决现代电路设计的多学科性质和计算复杂性方面变得无效，并且在某些情况下已经过时。目前，高速电路没有被商业电路仿真器适当地建模，并且是集成电路设计中的主要瓶颈之一。高科技电子和通信业已成为加拿大经济的重要部门。为了在全球市场上保持竞争力，我们的行业必须更快地设计电路，提高精度和功能。本研究计划的目的是开发先进的建模和仿真算法，用于高速集成电路和微系统的有效和准确的分析和设计。这将通过扩展宏建模算法的范围来实现，以在统一的仿真电路环境中有效地对大型多端口分布式电磁系统进行建模。此外，将开发基于波形松弛的新的并行计算技术，以降低大规模集成电路的计算复杂度。重点将是开发交互式设计验证技术，使大型复杂的分布式电路的迭代和重复的信号和电源完整性分析。这将导致更好的电路设计、更短的设计周期和更低的成本。

Advances of integrated circuit technology have increased the design complexity and operating signal speeds of electronic devices and are placing significant demands on electronic design automation (EDA) tools to provide the same efficiency and accuracy. Reduced feature sizes, and increasing packing densities and operating frequencies require multidisciplinary design methodologies such as electrical, thermal and electromagnetic analysis to accurately model the signal and power integrity of high-speed circuits. With higher operating frequencies, signal integrity issues such as signal delay, distortion, crosstalk and attenuation dominate and significantly degrade circuit performance. These effects exist throughout the design process at the chip, packaging, printed-circuit-board and backplane levels. In general, distributed circuits are modeled using partial differential equations and when discretized produce large system of equations, which are computationally expensive to solve. Furthermore, due to the increased packing densities of integrated circuits, it is becoming essential to model highly coupled interconnect and power distribution networks with many ports. Consequently, the underlying algorithms of traditional EDA tools have become ineffective and in some cases obsolete in addressing the multidisciplinary nature and computational complexity of modern circuit designs. Currently, high-speed circuits is not modeled appropriately by commercial circuit simulators, and stands as one of the major bottlenecks in the design of integrated circuits. The high-tech electronic and communication industry have become important sectors to the Canadian economy. To remain competitive in global markets, our industries have to design circuits quicker with increased accuracy and functionality. The aim of this research proposal is to develop advanced modeling and simulation algorithms for efficient and accurate analysis and design of high-speed integrated circuits and microsystems. This will be achieved by extending the scope of macromodeling algorithms to efficiently model large multi-port distributed electromagnetic systems in a unified simulation circuit environment. Furthermore, new parallel computing techniques based on waveform relaxation will be developed to reduce the computational complexity of large-scale integrated circuits. The emphasis will be to develop interactive design verification techniques that will enable iterative and repetitive signal and power integrity analysis of large complicated distributed circuits. This will lead to better circuit designs, shorter design cycles and lower costs.