Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache
Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache
复制标题
易失性 STT-RAM 缓存的编译器辅助刷新最小化
DOI：
10.1109/tc.2014.2360527
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发表时间：
2015-08
影响因子：
3.7
通讯作者：
Chun Jason Xue
中科院分区：
文献类型：
--
作者：
Yiran Chen;Yiran Chen;Chun Jason Xue;Chun Jason Xue
自旋转移扭矩RAM （STT-RAM）由于具有高存储密度和超低泄漏功率等优点，被提出用于构建片上高速缓存。然而，长写延迟和高写能量是STT-RAM面临的两大挑战。最近，研究人员提出通过放宽STT-RAM的非易失性来提高其写入性能。为了避免数据波动造成的数据丢失，提出了数据刷新方案。但是，刷新操作会消耗额外的开销。在本文中，我们建议通过在编译时重新安排程序数据布局来显著减少刷新操作的次数。为了进一步减少刷新次数，还提出了N-refresh方案。实验结果表明，平均而言，提出的方法可以减少84.2%的刷新操作次数，将易失性STT-RAM缓存的动态能耗降低38.0%，而性能下降仅为4.1%。
Spin-transfer torque RAM (STT-RAM) has been proposed to build on-chip caches because of its attractive features such as high storage density and ultra low leakage power. However, long write latency and high write energy are the two challenges for STT-RAM. Recently, researchers propose to improve the write performance of STT-RAM by relaxing its non-volatility property. To avoid data losses resulting from volatility, refresh schemes have been proposed. However, refresh operations consume additional overhead. In this paper, we propose to significantly reduce the number of refresh operations through re-arranging program data layout at compilation time. An N-refresh scheme is also proposed to further reduce the number of refreshes. Experimental results show that, on average, the proposed methods can reduce the number of refresh operations by 84.2 percent, and reduce the dynamic energy consumption by 38.0 percent for volatile STT-RAM caches while incurring only 4.1 percent performance degradation.
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DOI：
10.1109/hpca.2009.4798259
发表时间：
2009-03
期刊：
2009 IEEE 15th International Symposium on High Performance Computer Architecture
影响因子：
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作者：
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影响因子：
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DOI：
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发表时间：
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期刊：
2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
影响因子：
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DOI：
10.1145/280756.280792
发表时间：
1998-08
期刊：
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影响因子：
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作者：
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DOI：
10.1145/1391469.1391610
发表时间：
2008-06
期刊：
2008 45th ACM/IEEE Design Automation Conference
影响因子：
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作者：
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