Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.
Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.
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在0.5μmCMOS铸造过程中固态纳米孔的整合。
DOI：
10.1088/0957-4484/24/15/155501
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发表时间：
2013-04-19
期刊：
影响因子：
3.5
通讯作者：
Theogarajan L
中科院分区：
文献类型：
--
作者：
Uddin A;Yemenicioglu S;Chen CH;Corigliano E;Milaninia K;Theogarajan L
高带宽和低噪声的纳米孔传感器和检测电子设备是实现单DNA碱基分辨率的关键。实现这一目标的一个潜在方法是将固态纳米孔集成到一个cmos平台中，靠近偏置电极和定制设计的放大器电子设备。在这里，我们报告了一种商用互补金属氧化物半导体恒电位器芯片中固态纳米孔器件的集成，该芯片采用安森美半导体的0.5μm工艺。利用上述工艺中可获得的N+多晶硅/二氧化硅/N+多晶硅电容器结构，通过后CMOS微机械加工制备了包含电极的纳米孔膜。纳米孔是通过在透射电子显微镜中钻孔并通过原子层沉积来收缩在cmos工艺中创建的。我们还描述了一种批量制作方法，通过电子束光刻和原子层沉积在与CMOS兼容的晶片上大量加工直径小于10 nm的电极嵌入的纳米孔。通过测试片上电路的电气功能，验证了我们的制造工艺的CMOS兼容性。我们观察到由于离子通过SiO_2膜的扩散，导致了CMOS纳米孔器件的高电流泄漏。为了防止这种泄漏，我们在膜上涂上了氧化铝，这是防止碱性离子的有效扩散屏障。与SiO_2和SiN_x相比，所得到的纳米孔器件还表现出更高的稳健性和更低的1/f噪声。此外，我们还提出了一种适用于我们的低电容纳米孔器件的理论模型，该模型与实验值吻合较好。此外，还利用48.5kBP的λ-DNA进行了易位研究的实验和理论模型，以证明包覆了Al_2O_3的芯片上孔的功能性。
High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.
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影响因子：
2.5
作者：
Iakoubovskii, K.;Mitsuishi, K.;Furuya, K.
通讯作者：
Furuya, K.
影响因子：
3.1
作者：
HUNG, KK;KO, PK;CHENG, YC
通讯作者：
CHENG, YC
影响因子：
3.5
作者：
Kowalczyk, Stefan W.;Grosberg, Alexander Y.;Dekker, Cees
通讯作者：
Dekker, Cees
影响因子：
41.2
作者：
Li, JL;Gershow, M;Golovchenko, JA
通讯作者：
Golovchenko, JA
DOI：
10.1073/pnas.93.24.13770
发表时间：
1996-11-26
影响因子：
11.1
作者：
Kasianowicz, JJ;Brandin, E;Deamer, DW
通讯作者：
Deamer, DW