Design and Implement of Low Power Consumption SRAM Based on Single Port Sense Amplifier in 65 nm
Design and Implement of Low Power Consumption SRAM Based on Single Port Sense Amplifier in 65 nm
复制标题
65 nm基于单端口读出放大器的低功耗SRAM的设计与实现
DOI：
10.4236/jcc.2015.311026
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发表时间：
2015-11
期刊：
影响因子：
--
通讯作者：
Xi Peng
中科院分区：
文献类型：
--
作者：
Shunrui Li;Jianjun Chen;Zuocheng Xing;Jinjin Shao;Xi Peng
随着集成电路的快速发展[1]，低功耗已成为设计者在芯片设计中不断追求的目标。由于内存几乎占据了芯片的面积，降低内存功耗将显著降低芯片的整体功耗；根据ISSCC 2014年关于技术趋势讨论的报告，超低功耗SRAM设计有两点：1)为SRAM的每个关键模块设计更有效的静态和动态电源控制电路；2)确保在VDD min非常低的情况下，SRAM能够可靠稳定地运行。本文充分利用了8T单元的可靠性，单端口读出放大器解决了传统8T单元结构中存在的问题，使新结构的存储器在更深层次上仍然保持了良好的性能和较低的功耗。与商业编译生成的SRAM相比，由于SS角的性能损失不超过10%，整体功耗可以降低54.2%，可以达到很好的低功耗设计效果。
With the rapid development of integrated circuits [1], low power consumption has become a constant pursuiting goal of the designer in chip design. As the memory almost takes up the area of the chip, reducing memory power consumption will significantly reduce the overall power consumption of the chip; according to ISSCC’s 2014 report about technology trends discussions, there two points of the super-low power SRAM design: 1) design a more effective static and dynamic power control circuit for each key module of SRAM; 2) ensure that in the case of the very low VDD min, SRAM can operating reliably and stably. This paper makes full use reliable of 8T cell, and the single-port sense amplifier has solved problems in the traditional 8T cell structure, making the new structure of the memory at a greater depth still maintain good performance and lower power consumption. Compared with the designed SRAM the SRAM generated by commercial compiler, as the performance loss at SS corner does not exceed 10%, the whole power consumption could be reduced by 54.2%, which can achieve a very good effect of low-power design.
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影响因子：
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作者：
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通讯作者：
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期刊：
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期刊：
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