Sub-10 Nanometer Feature Size in Silicon Using Thermal Scanning Probe Lithography.

Sub-10 Nanometer Feature Size in Silicon Using Thermal Scanning Probe Lithography.
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DOI:
10.1021/acsnano.7b06307
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发表时间:
2017-12-26
期刊:
影响因子:
17.1
通讯作者:
Knoll AW
Knoll AW
中科院分区:
材料科学1区
文献类型:
--
作者:
Ryu Cho YK;Rawlings CD;Wolf H;Spieser M;Bisig S;Reidt S;Sousa M;Khanal SR;Jacobs TDB;Knoll AW

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High-resolution lithography often involves thin resist layers which pose a challenge for pattern characterization. Direct evidence that the pattern was well-defined and can be used for device fabrication is provided if a successful pattern transfer is demonstrated. In the case of thermal scanning probe lithography (t-SPL), highest resolutions are achieved for shallow patterns. In this work, we study the transfer reliability and the achievable resolution as a function of applied temperature and force. Pattern transfer was reliable if a pattern depth of more than 3 nm was reached and the walls between the patterned lines were slightly elevated. Using this geometry as a benchmark, we studied the formation of 10–20 nm half-pitch dense lines as a function of the applied force and temperature. We found that the best pattern geometry is obtained at a heater temperature of ∼600 °C, which is below or close to the transition from mechanical indentation to thermal evaporation. At this temperature, there still is considerable plastic deformation of the resist, which leads to a reduction of the pattern depth at tight pitch and therefore limits the achievable resolution. By optimizing patterning conditions, we achieved 11 nm half-pitch dense lines in the HM8006 transfer layer and 14 nm half-pitch dense lines and L-lines in silicon. For the 14 nm half-pitch lines in silicon, we measured a line edge roughness of 2.6 nm (3σ) and a feature size of the patterned walls of 7 nm.
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