NoC-enabled software/hardware co-design framework for accelerating k-mer counting

NoC-enabled software/hardware co-design framework for accelerating k-mer counting
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支持 NoC 的软件/硬件协同设计框架,用于加速 k-mer 计数

DOI:
10.1145/3313231.3352367
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发表时间:
2019
期刊:
Proc. IEEE/ACM International Symposium on Networks-on-Chip (NOCS'19
影响因子:
--
通讯作者:
Krishnamoorthy, Sriram
Krishnamoorthy, Sriram
中科院分区:
--
文献类型:
--
作者:
Joardar, Biresh Kumar;Ghosh, Priyanka;Pande, Partha Pratim;Kalyanaraman, Ananth;Krishnamoorthy, Sriram

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DNA和蛋白质序列中的计数链(固定长度的子串)产生不均匀和不规则的记忆访问模式。内存中处理(PIM)体系结构具有显著降低与此类频繁和不规则内存访问相关的开销的潜力。然而,现有的k-mercounting算法并没有充分利用PIM架构的优势。此外,由于热约束,在传统的PIM设计中允许的功率预算是有限的。此外,k-mercounting会产生不平衡和长距离的流量模式,需要由高效的片上网络(NoC)来处理。在本文中,我们提出了一个支持noc的软件/硬件协同设计框架来实现高性能的销售。所提出的架构可以实现更多的计算能力,内核/内存之间的高效通信-所有这些都不会产生热瓶颈;而软件组件则提供了更多的内存中机会来利用PIM,并在NoC设计中提供帮助。实验结果表明,所提出的架构比使用混合内存立方体(HMC)的最先进的k-mercounting软件实现高出7.14倍,同时允许显着更高的功耗预算。
Countingk-mers(substrings of fixed lengthk) in DNA and protein sequences generate non-uniform and irregular memory access patterns. Processing-in-Memory (PIM) architectures have the potential to significantly reduce the overheads associated with such frequent and irregular memory accesses. However, existingk-mercounting algorithms are not designed to exploit the advantages of PIM architectures. Furthermore, owing to thermal constraints, the allowable power budget is limited in conventional PIM designs. Moreover,k-mercounting generates unbalanced and long-range traffic patterns that need to be handled by an efficient Network-on-Chip (NoC). In this paper, we present an NoC-enabled software/hardware co-design framework to implement high-performancek-mercounting. The proposed architecture enables more computational power, efficient communication between cores/memory - all without creating a thermal bottleneck; while the software component exposes more in-memory opportunities to exploit the PIM and aids in the NoC design. Experimental results show that the proposed architecture outperforms a state-of-the-art software implementation ofk-mercounting utilizing Hybrid Memory Cube (HMC), by up to 7.14X, while allowing significantly higher power budgets.
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