Simulation study of an ultra-low specific on-resistance high-voltage pLDMOS with self-biased accumulation layer
Simulation study of an ultra-low specific on-resistance high-voltage pLDMOS with self-biased accumulation layer
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具有自偏置累积层的超低比导通电阻高压pLDMOS仿真研究
DOI：
10.1587/elex.16.20190673
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发表时间：
2020
影响因子：
0.8
通讯作者：
HaiMeng Huang
中科院分区：
文献类型：
--
作者：
Bo Yi;Yi Feng Peng;Qing Zhao;MouFu Kong;JunJi Cheng;HaiMeng Huang
本文提出了一种具有自偏置积累层的高压p沟道横向扩散金属氧化物半导体晶体管（pLDMOS）。在薄绝缘层上形成多晶硅层，多晶硅层位于P-漂移区的表面。在导通状态下，在多晶硅上施加自动获得的负电压，以在P漂移区表面诱导空穴积累层。因此，可以显著降低比导通电阻（Ron，sp）。此外，可以通过选择不同的绝缘体材料来增加P-漂移上的栅极绝缘体的介电常数。因此，由于更多的空穴在P-漂移的表面处积累，可以进一步减小R on，sp。模拟结果表明，与p型三重RESURF硅限相比，pLDMOS的导通电阻（Ron，sp）可降低62.3%~ 82.5%。与扩展栅pLDMOS（EG-pLDMOS）和传统pLDMOS相比，所提出的pLDMOS的瞬态品质因数（FOM）显著提高了几倍到10倍，静态品质因数（FOM）提高了几倍。
In this letter, a high-voltage p-channel Lateral Diffused Metal Oxide Semiconductor Transistor (pLDMOS) with self-biased accumulation layer is proposed. A poly-silicon layer is formed on the thin insulator layer , which locates at the surface of the P-drift region. During on-state, an automatically obtained negative voltage is applied on the poly-silicon to induce a hole accumulation layer at the surface of the P-drift region. Therefore, the specific on-resistance ( R on,sp ) can be significantly reduced. Moreover, the permittivity of the gate insulator on the P-drift can be increased by selecting different insulator materials. Thus, the R on,sp can be further reduced due to more holes being accumulated at the surface of the P-drift. The simulation results shows that the R on,sp of the proposed pLDMOS can be dramatically reduced by 62.3% to 82.5% compared with that of the p-type Triple RESURF silicon limit. For the proposed pLDMOS, the transient Figure of Merit (FOM) is significantly improved by several to 10 times and the static Figure of Merit (FOM) is improved by several times compared with those of an Extended Gate pLDMOS (EG-pLDMOS) and a conventional pLDMOS.
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影响因子：
3.1
作者：
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通讯作者：
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影响因子：
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作者：
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通讯作者：
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影响因子：
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作者：
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DOI：
10.1109/ispsd.2011.5890784
发表时间：
2011-05
期刊：
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs
影响因子：
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作者：
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通讯作者：
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影响因子：
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