Overgrowth and characterization of (11-22) semi-polar GaN on (113) silicon with a two-step method

Overgrowth and characterization of (11-22) semi-polar GaN on (113) silicon with a two-step method
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采用两步法在 (113) 硅上过度生长和表征 (11-22) 半极性 GaN

DOI:
10.1088/1361-6641/ab08bf
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发表时间:
2019
影响因子:
1.9
通讯作者:
Cai Y
Cai Y
中科院分区:
工程技术4区
文献类型:
--
作者:
Cai Y

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我们开发了一种两步法,用于在图案化 (113) 硅衬底上生长半极性 (11-22) GaN,该方法有效地消除了高温下 Ga 回熔蚀刻,这是最具挑战性的问题之一。采用标准光刻技术将(113)硅衬底图案化为沟槽,然后进行各向异性化学刻蚀,除了未刻蚀的(113)刻面外,还形成相对于c轴倾斜角度为58°的(111)刻面。随后在图案化的硅上外延生长厚的AlN层以覆盖所有小面,确保消除回熔,随后仅在(113)小面上选择性地沉积SiO 2 掩模。进一步的 GaN 过生长仅在暴露的 (111) 面上进行,形成沿垂直方向具有高晶体质量的 (11-22) 半极性 GaN。已观察到室温下的受激发射阈值较低。低温光致发光测量证实基底堆垛层错密度显着降低。该方法提供了一种有效抑制Ga回熔蚀刻问题的有前景的方法,这对于需要高生长温度的半极性GaN上的Al(Ga)N生长尤其重要。所提出的结果对于开发硅上电子和光子学的单片片上集成至关重要。
A two-step approach has been developed for the growth of semi-polar (11–22) GaN on patterned (113) silicon substrates, which effectively eliminates Ga melt-back etching at a high temperature, one of the most challenging issues. A (113) Si substrate is patterned into groove trenches by means of using a standard photolithography technique and then anisotropic chemical etching, forming (111) facets with an inclination angle of 58 with respect to c-axis in addition to the un-etched (113) facets. A thick AlN layer is subsequently epitaxially grown on the patterned silicon to cover all the facets ensuring to eliminate the melt-back, followed by selectively depositing SiO 2 masks on the (113) facets only. Further GaN overgrowth is performed only on the exposed (111) facets, forming (11–22) semi-polar GaN with high crystal quality along the vertical direction. Stimulated emission at room temperature has been observed with a low threshold. Low-temperature photoluminescence measurements confirm a significant reduction in basal stacking faults density. This method provides a promising approach to effectively suppress the Ga melt-back etching issue, which is particularly important for Al (Ga) N growth on semi-polar GaN that requires a high growth temperature. The presented results are crucially important for developing monolithic on-chip integration of electronics and photonics on silicon.
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