Memory Hierarchy in MIMD Multiprocessors

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The research team intends to study the management of the memory hierarchy in MIMD multiprocessors. The recent technological explosion has allowed the inclusion of large and fast memories in many levels of the memory hierarchy. The management of this hierarchy is quite well understood in a uniprocessor environment but newer challenges present themselves in a multiprocessor system. One of these challenges is the cache coherence problem. They will continue previous studies on cache coherence in shared-bus systems (enhancement of existing solutions with software hints, evaluation on specific applications) and in interconnected systems (they will model a wide spectrum of solutions). They will extend these studies with those pertaining to the design and management of the memory hierarchy in high-performance systems. This will include multilevel caches (architectural choices, design and evaluation of protocols) and systems where not all levels are managed under the virtual memory concept (use of planned transfers of data between memory levels with compiler and programmer assists). Finally, they will try to evaluate qualitatively and quantitatively the numerous possibilities for the location of the translation buffer from the conventional real caches to those architectures using virtual address caches.