Using Predictor Paradigms to Enhance Memory Hierarchy Performance

使用预测器范式增强内存层次结构性能

• 批准号: 0072948
• 负责人: Jean-Loup Baer
• 金额: $ 44.84万
• 依托单位: University of Washington
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2000
• 资助国家: 美国
• 起止时间: 2000-07-01 至 2003-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0072948&HistoricalAwards=false
• 关键词: Using; Predictor; Paradigms; Enhance; Memory

The focus of this research is the design and evaluation of hardware assists and software profiling techniques that allow better utilization and performance of the memory hierarchy of high-performance systems. The overall goal is to lessen the impact of the increasing speed discrepency between processors and the various levels of the memory hierarchy.The research methodology will compare the results of offline, optimal algorithms with algorithms that can be feasibly implemented in a memory system, to guage the performance increase possible from prediction triggering, indexing, prediction mechanisms, and feedback. This methodology will be applied to three specific problems: Dynamic line size choice, replacement algorithms for caches with large associativities, and prefetching in lower levels of the memory hierarchy.

本研究的重点是硬件辅助和软件分析技术，允许更好地利用和高性能系统的内存层次结构的性能的设计和评估。 总体目标是减少处理器和存储器层次结构的各个级别之间的速度差异的影响，研究方法将比较离线的最佳算法与可以在存储器系统中可行地实现的算法的结果，以衡量从预测触发，索引，预测机制和反馈可能带来的性能提高。 这种方法将被应用到三个具体的问题：动态行大小的选择，替换算法的高速缓存与大associativities，并在较低层次的存储器层次结构的预取。