Memory Hierarchy in High-Performance Systems

首席研究员继续对设计进行研究， 评估高性能系统的内存层次结构。 单处理器和共享内存多处理器将 研究了 这些研究将涵盖创新的建筑特色， 编译器支持、协议和硬件同步 几种并行编程模型的原语。 在单处理器的情况下，基于硬件的预加载方案， 应该减少数据缓存中的未命中数量， 研究了 对该硬件功能的更好支持还将 追究 在多处理器的情况下，各种协议和可能的 增强的同步原语，以满足几种一致性 将对模型进行研究。 目标是减少 性能降低组件（内存延迟大、处理器 停止，网络流量）所产生的访问共享 变量 其他主题包括体系结构功能，例如 使用互连网络或其一个级别作为 内存层次结构的组成部分。 跟踪驱动的仿真将是性能评估的选择 工具. 计算机密集型程序，具有从 科学和CAD工具的应用将被仪器化。

The principal investigator continues his research on the design and evaluation of the memory hierarchy of high-performance systems. Uniprocessors as well as shared-memory multiprocessors will be studied. The studies will cover innovative architectural features, compiler support, and protocols and hardware synchronization primitives for several parallel programming models. In case of uniprocessors, a hardware-based preloading scheme that should reduce the number of misses in data caches, will be investigated. Compiler support for this hardware function will also be investigated. In the case of multiprocessors, various protocols and possibly enhanced synchronization primitives to cater to several consistency models will be investigated. The goal is to reduce the impact of the performance degradation components (large memory latency, processor stalling, network traffic) arising from the access to shared variables. Other topics include architectural features such as the use of the interconnection network, or one of its levels, as a component of the memory hierarchy. Trace-driven simulation will be the choice performance evaluation tool. Computer-intensive programs with large data sets drawn from scientific and CAD tool application will be instrumented.