Memory Hierarchy in High-Performance Systems

主要研究人员继续研究高性能系统的存储器层次结构的设计和评估。将学习单处理器和共享内存多处理器。这些研究将涵盖创新的体系结构特征、编译器支持，以及用于几个并行编程模型的协议和硬件同步原语。在单处理器的情况下，将研究基于硬件的预加载方案，该方案应该减少数据高速缓存中的未命中数量。还将调查编译器对此硬件函数的支持。在多处理器的情况下，将研究各种协议和可能增强的同步原语以迎合几个一致性模型。其目标是减少因访问共享变量而引起的性能下降组件(大内存延迟、处理器停顿、网络流量)的影响。其他主题包括体系结构特征，例如使用互连网络或其级别之一作为存储器层次结构的组件。轨迹驱动的仿真将是性能评估的首选工具。从科学和CAD工具应用程序中提取大量数据集的计算机密集型程序将被仪表化。

The principal investigator continues his research on the design and evaluation of the memory hierarchy of high-performance systems. Uniprocessors as well as shared-memory multiprocessors will be studied. The studies will cover innovative architectural features, compiler support, and protocols and hardware synchronization primitives for several parallel programming models. In case of uniprocessors, a hardware-based preloading scheme that should reduce the number of misses in data caches, will be investigated. Compiler support for this hardware function will also be investigated. In the case of multiprocessors, various protocols and possibly enhanced synchronization primitives to cater to several consistency models will be investigated. The goal is to reduce the impact of the performance degradation components (large memory latency, processor stalling, network traffic) arising from the access to shared variables. Other topics include architectural features such as the use of the interconnection network, or one of its levels, as a component of the memory hierarchy. Trace-driven simulation will be the choice performance evaluation tool. Computer-intensive programs with large data sets drawn from scientific and CAD tool application will be instrumented.