Memory Hierarchy in High-Performance Systems

首席研究员继续研究高性能系统的内存层次的设计和评估。将研究单处理器以及共享内存多处理器。这些研究将涵盖一些并行编程模型的创新架构特性、编译器支持、协议和硬件同步原语。在单处理器的情况下，将研究一种基于硬件的预加载方案，该方案应减少数据缓存中的丢失次数。还将研究编译器对该硬件功能的支持。在多处理器的情况下，将研究各种协议和可能增强的同步原语，以满足几种一致性模型。目标是减少由于访问共享变量而产生的性能降低组件（大内存延迟、处理器停滞、网络流量）的影响。其他主题包括架构特性，如互连网络的使用，或其级别之一，作为内存层次结构的一个组件。轨迹驱动仿真将成为性能评估的首选工具。从科学和CAD工具应用中绘制的具有大数据集的计算机密集型程序将被仪器化。

The principal investigator continues his research on the design and evaluation of the memory hierarchy of high-performance systems. Uniprocessors as well as shared-memory multiprocessors will be studied. The studies will cover innovative architectural features, compiler support, and protocols and hardware synchronization primitives for several parallel programming models. In case of uniprocessors, a hardware-based preloading scheme that should reduce the number of misses in data caches, will be investigated. Compiler support for this hardware function will also be investigated. In the case of multiprocessors, various protocols and possibly enhanced synchronization primitives to cater to several consistency models will be investigated. The goal is to reduce the impact of the performance degradation components (large memory latency, processor stalling, network traffic) arising from the access to shared variables. Other topics include architectural features such as the use of the interconnection network, or one of its levels, as a component of the memory hierarchy. Trace-driven simulation will be the choice performance evaluation tool. Computer-intensive programs with large data sets drawn from scientific and CAD tool application will be instrumented.