Improving the Performance of the Memory Hierarchy

提高内存层次结构的性能

• 批准号: 9700970
• 负责人: Jean-Loup Baer
• 金额: $ 34.03万
• 依托单位: University of Washington
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1997
• 资助国家: 美国
• 起止时间: 1997-07-01 至 2000-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9700970&HistoricalAwards=false
• 关键词: Improving; Performance; Memory; Hierarchy

The goal of this research is to lessen the impact of the increasing speed disadvantage of memories when compared to processors. The focus in this project will be the design and evaluation of profiling techniques and hardware assists to allow better utilization and performance of the memory hierarchy. The planned efforts are to (1) improve the efficiency of on-chip caches by using better code and data placement informed by profiling; (2) determine when it is advantageous to bypass the data cache; (3) take advantage of page and burst modes of modern DRAMs; (4) investigate methods to reduce data latency by prefetching; and (5) design hardware assists at the main memory interface for compaction or partial transfer of data. These techniques will be evaluated using trace-driven simulations or profiling of binary executables for SPEC benchmarks and commercial applications.

这项研究的目标是减少内存与处理器相比速度不断提高的劣势带来的影响。该项目的重点将是分析技术和硬件辅助的设计和评估，以便更好地利用和提高内存层次结构的性能。计划的努力是：(1)通过使用由剖析通知的更好的代码和数据放置来提高片上高速缓存的效率；(2)确定何时绕过数据高速缓存是有利的；(3)利用现代DRAM的页面和突发模式；(4)研究通过预取来减少数据延迟的方法；以及(5)在主存储器接口上设计硬件辅助以用于数据的压缩或部分传输。这些技术将使用跟踪驱动的模拟或对SPEC基准测试和商业应用程序的二进制可执行文件进行分析来进行评估。