Memory Management in Shared-Memory Multiprocessors

共享内存多处理器中的内存管理

• 批准号: 8904190
• 负责人: Jean-Loup Baer
• 金额: $ 18.9万
• 依托单位: University of Washington
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1989
• 资助国家: 美国
• 起止时间: 1989-07-15 至 1991-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=8904190&HistoricalAwards=false
• 关键词: Memory; Management; Shared; Multiprocessors

This is a continuation of the PI's research on the design of small to medium scale shared-memory multiprocessors where the number of CPU's ranges from a very few to several hundreds. The emphasis is on the management of the memory hierarchy. Innovative architectural features, such as multi-level cache hierarchies and interconnection networks with memory in the switches are studied. An important component of the research is providing qualitative and quantitative evaluations through trace-driven and synthetic simulations. In the case of multi-level cache hierarchies, the emphasis is on the design and evaluation of a two level virtual-real cache hierarchy, the effect of inclusion properties on the protocols for cache coherence and performance in bus-hierarchy based architectures, and on techniques for speeding up trace driven simulation (inclusion properties, trace reduction, parallel simulation). A second area of research is techniques and architectural enhancements to reduce the memory latency in architectures where processors and memory modules are connected by a multi-stage interconnection network. The first part of the research considers caching as a viable alternative and studies improved self-invalidation cache coherence schemes and compares their performance and cost with those of previously published protocols. The second part continues the PI's investigation of the introduction of memory in the switches of the interconnection network.

这是PI对设计中小型共享内存多处理器的研究的继续，其中CPU的数量从很少到几百个不等。重点放在内存层次的管理上。研究了创新的体系结构特征，如多级缓存层次结构和交换机中具有存储器的互连网络。这项研究的一个重要组成部分是通过轨迹驱动和综合模拟提供定性和定量的评估。在多级高速缓存层次结构的情况下，重点是设计和评估两级虚拟-真实高速缓存层次结构，包含属性对基于总线层次结构的高速缓存一致性和性能协议的影响，以及用于加速跟踪驱动的模拟(包含属性、跟踪缩减、并行模拟)的技术。第二个研究领域是减少处理器和存储模块通过多级互连网络连接的体系结构中的存储等待时间的技术和体系结构增强。研究的第一部分认为缓存是一种可行的替代方案，研究了改进的自失效缓存一致性方案，并将它们的性能和成本与以前公布的协议进行了比较。第二部分继续PI对在互连网络的交换机中引入存储器的调查。