Research Initiation: Testing and Fault Tolerance of MOSFET and MODFET Memories

这项研究是为了了解，通过模拟和 实验研究，新的高密度的破坏机理， 以及高速存储器技术，如硅DRAM （动态随机存取存储器）， 砷化镓高电子迁移率晶体管 SRAM（静态随机存取存储器）和CMOS（互补 金属氧化物半导体）神经网络关联存储器。 基于这种故障特征，Mazumder博士建议 制定适当的测试方法。 他的研究是在三个 阶段。 第一阶段研究了一种新的片上双误差 用于多兆位硅DRAM的校正电路。 这 电路将纠正双位/字线软错误， 不能通过传统的纠错电路来纠正。 在第二阶段，他正在开发一个全面的故障模型 高速GaAsHEMT参数测试算法 静态RAM;并正在研究内置自测试电路， 生成算法。 第三个问题是如何测试神经 网络联想记忆与纠错研究 这种记忆的能力，在存在故障的情况下， 错误的输入数据。

This research is to understand, through simulation and experimental studies, the failure mechanisms of new high-density and high-speed memory technologies such as silicon DRAM's (dynamic random-access memory) with trench-type cell capacitor, GaAs (Gallium Arsenide) HEMT (High-Electron Mobility Transistor) SRAM's (static random-access memory) and CMOS (complementary metal oxide semiconductor) neural network associative memories. Based in this fault characterization, Dr. Mazumder proposes to develop appropriate test methodologies. His research is in three phases. The first phase investigates a new on-chip double-error correction circuit for the multi-megabit Silicon DRAM. This circuit will correct double-bit/word-line soft errors that cannot be corrected by conventional error correcting circuits. In the second phase, he is developing a comprehensive fault model and efficient parametric test algorithms for high-speed GaAs HEMT Static RAM; and is investigating built-in self-test circuits to generate the algorithms. The third problem is how to test neural network associative memories and a study of error correction capabilities of such memories in the presence of faulty components and erroneous input data.