Theory, Design, Implementation and Automatic Compilation of Adaptive Circuits for Built-in Self-Repairable USLI/MCM Chips

这项研究的目标是开发一种创新和统一的方法来设计可自修复的超大规模集成电路(ULSI)和多芯片模块(MCM)芯片。这项研究将利用由简单阈值器件互连的可编程电阻网络组成的自适应电路所提供的组合优化能力，目的是为硬件设备增加自修复能力。拟议的研究将分三个阶段进行。在第一阶段，将建立规则阵列逻辑和非结构化随机逻辑重排问题的理论模型，并进行明示仿真以测量自适应自修复电路的性能。在第二阶段，将使用CMOS技术设计自适应电路，并将制造实验芯片并进行测试，以此作为“概念验证”。在第三阶段，将开发软件，使所提出的自适应自校正电路可以由VLSI/CAD软件自动综合，并在宏块中进行合并。该项目开启了一个新的研究领域，是内建自测试(BIST)和可测试性设计(DFT)领域正在进行的工作的自然续篇。

The goal of this research is to develop an innovative and unified methodology for designing self-repairable ultra-large integated (ULSI) circuits and multi-chip module (MCM) chips. This research will exploit the combinatorial optimization capabilities offered by adaptive circuits consisting of simple threshold devices interconnected programmable resistive networks for the purpose of adding a self-repair capability to hardware devices. The proposed research will be conducted in three phases. In the first phase, theoretical models for both regular array logic and unstructured random logic repar problems will be developed, and entensive simulations will be performed to measure the performance of the adaptive self-repair circuits. In the second phase, adaptive circuits will be designed using CMOS technology, and experimental chips willbe fabricated and tested as "proofs. of concept." In the third phase, software will be developed to allow the proposed adaptive bult-in-self-repar circuits to be automatically synthesized by VLSI/CAD software and invorporated within macro blocks. This project initiates a new area of research that is a natural sequel to the on-going works in the fields of Built-In- Self-Testing (BIST) and Design for Testability (DFT).