Theory, Design, Implementation and Automatic Compilation of Adaptive Circuits for Built-in Self-Repairable USLI/MCM Chips

本研究的目标是发展一种创新的和统一的方法，设计自修复超大规模集成电路（ULSI）和多芯片模块（MCM）芯片。 本研究将利用自适应电路提供的组合优化能力，由简单的阈值器件互连的可编程电阻网络的目的，增加了自修复能力的硬件设备。 拟议的研究将分三个阶段进行。 在第一阶段，将开发规则阵列逻辑和非结构化随机逻辑修复问题的理论模型，并进行广泛的模拟来测量自适应自修复电路的性能。 第二阶段将利用CMOS工艺设计自适应电路，并制作实验芯片作为“验证”。的概念。“在第三阶段，我们会开发软件，让建议的自适应自修复电路可以由超大规模集成电路/计算机辅助设计软件自动合成，并在宏块内进行转换。 该项目开创了一个新的研究领域，是内建自测试（BIST）和可测试性设计（DFT）领域正在进行的工作的自然续集。

The goal of this research is to develop an innovative and unified methodology for designing self-repairable ultra-large integated (ULSI) circuits and multi-chip module (MCM) chips. This research will exploit the combinatorial optimization capabilities offered by adaptive circuits consisting of simple threshold devices interconnected programmable resistive networks for the purpose of adding a self-repair capability to hardware devices. The proposed research will be conducted in three phases. In the first phase, theoretical models for both regular array logic and unstructured random logic repar problems will be developed, and entensive simulations will be performed to measure the performance of the adaptive self-repair circuits. In the second phase, adaptive circuits will be designed using CMOS technology, and experimental chips willbe fabricated and tested as "proofs. of concept." In the third phase, software will be developed to allow the proposed adaptive bult-in-self-repar circuits to be automatically synthesized by VLSI/CAD software and invorporated within macro blocks. This project initiates a new area of research that is a natural sequel to the on-going works in the fields of Built-In- Self-Testing (BIST) and Design for Testability (DFT).