Design of Fabrication of Electronic Neural Networks for Built-in Self-Repair of VLSI Chips with Embedded Logic Memory Arrays

本研究是利用组合优化的能力， 设计出解决修复问题的算法 在IC芯片中。 两类阵列修复问题正在 考察 第一种是通过替换行和列进行修复 (as在存储器阵列中）。 第二种是通过更换 单个单元（如脉动阵列和迭代逻辑）。 分析了阵列修复问题的理论模型， 模拟来衡量神经修复算法的性能。 电子神经网络将执行神经修复 用于记忆、脉动和迭代阵列的算法正在被 设计和制作

This research is using the combinatorial optimization capabilities of neural networks to devise algorithms for solving repair problems in IC chips. Two classes of array repair problems are being examined. The first is repair by replacement of rows and columns (as in memory arrays). The second is repair by replacement of individual cells (as in systolic arrays and iterative logic). Theoretical models of array repair problems are being analyzed and simulated to measure the performance of neural repair algorithms. Electronic neural networks that will execute the neural repair algorithms for memory, systolic and iterative arrays are being designed and fabricated.