RIA: Memory Architectures for Parallel Processing

这项研究的主要目标是提高用于科学和工程计算的计算机体系结构的性能。更具体地说，科学应用的特征与集成电路技术的趋势相结合表明，存储器系统的性能将很快成为这些体系结构中的处理瓶颈。研究的重点是提高存储系统性能的相关问题。调查的第一阶段研究了科学代码中数据获取的特点。了解向量和数组在应用程序中的用法是设计高效内存结构的先决条件。调查的第二部分考虑了揭示内存体系结构对系统软件的好处。特别是，将对最近提出在主存储器中使用动态存储方案的工作进行扩展。这种使用编译时和运行时生成的程序行为知识来动态优化存储器体系结构的技术将在实验、使用模拟和理论上进行考虑。重点放在使用存储方案以减少对共享存储器模块和处理器-存储器互连网络的争用。同时，将开发一套工具来提供主存体系结构的交互动画和模拟。

The primary objective of this investigation is to improve the performance of computer architectures used for scientific and engineering computation. More specifically, characteristics of scientific applications combined, with trends in integrated circuit technology indicate that memory system performance will soon be, if it is not already, the processing bottleneck in these architectures. The research focuses on issues related to the improvement of memory system performance. The first phase of the investigation studies characteristics of data access in scientific codes. An understanding of vector and array usage in applications is a prerequisite to designing efficient memory structures. The second part of the investigation considers the benefits of uncovering the memory architecture to system software. In particular, the recent work proposing the use of dynamic storage schemes in main memory will be expanded upon. This technique of using compile time and run time generated knowledge of program behavior to dynamically optimize the memory architecture will be considered experimentally, using simulation, and theoretically. Emphasis is placed on the use of storage schemes to reduce contention for shared memory modules and the processor-memory interconnection network. Concurrently, a set of tools to provide interactive animation and simulation of main memory architectures will be developed.