Programmable memory systems for manycore architectures

适用于众核架构的可编程内存系统

• 批准号: 402849-2011
• 负责人: Shriraman, Arrvindh
• 金额: $ 2.4万
• 依托单位: Simon Fraser University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2017
• 资助国家: 加拿大
• 起止时间: 2017-01-01 至 2018-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=637711
• 关键词: Programmable; memory; systems; manycore; architectures

Multicore chips dominate the computing spectrum, replacing uniprocessors throughout the desktop, server, and mobile markets. In the future, manufacturers promise to deliver manycore chips which integrate 100s of diverse compute processors. An on-chip memory hierarchy needs to be carefully designed to ensure that the compute units are kept busy. Current memory hierarchies are hardware-managed with fixed policies for data management. This rigidity doesn't dovetail with the complex access patterns in modern applications and it has become challenging to effectively supply data to the large number of cores in a timely manner.In this project, we investigate an integrated hardware-software approach to managing the memoryhierarchy on future multicore and manycore architectures. Our thesis is that a flexible memoryhierarchy that provides basic primitives to the tune the storage organization will facilitate software to adapt memory system to the computation. Software will specify hints to hardware, such as (1) where toplace the data, which will exploit data locality and streamline the access to data and (2) what datato keep on-chip and how to share on-chip storage, which will improve the overall efficiency of on-chip storage.Driving applications for our work will be drawn from multiple sources, including collaborative efforts with university (and external) colleagues in artificial intelligence, bioinformatics, computer vision, data mining, transactional memory, and commercial server workloads. The proposed research develops technologies critical to improving the utility of manycore chips. Efficient manycore chips will enable the software industry to continue developing applications that span commerce, science, national security, and healthcare.

多核芯片在计算领域占据主导地位，在台式机、服务器和移动的市场上取代了单处理器。在未来，制造商承诺提供集成数百种不同计算处理器的众核芯片。片上存储器层次结构需要仔细设计，以确保计算单元保持忙碌。当前的存储器层次结构是用固定的数据管理策略进行硬件管理的。这种刚性与现代应用中复杂的访问模式不相吻合，并且及时有效地向大量核心提供数据变得具有挑战性。在本项目中，我们研究一种集成的硬件-软件方法来管理未来多核和众核架构上的内存层次结构。我们的论点是，一个灵活的内存层次结构，提供基本的原语来调整存储组织将有助于软件适应内存系统的计算。软件将为硬件指定提示，例如（1）将数据放置在何处，这将利用数据本地性并简化对数据的访问，以及（2）哪些数据将保留在芯片上以及如何共享芯片存储，这将提高芯片存储的整体效率。我们工作的驱动应用程序将来自多个来源，包括与大学（和外部）同事在人工智能，生物信息学，计算机视觉，数据挖掘，事务内存和商业服务器工作负载方面的合作。拟议中的研究开发了对提高众核芯片实用性至关重要的技术。高效的众核芯片将使软件行业能够继续开发涵盖商业、科学、国家安全和医疗保健的应用程序。