Programmable memory systems for manycore architectures

多核芯片在计算领域占据主导地位，在台式机、服务器和移动市场取代了单处理器。在未来，制造商承诺提供集成了数百个不同计算处理器的多核芯片。需要仔细设计片上存储器层次结构，以确保计算单元保持忙碌。当前的内存层次结构是硬件管理的，具有固定的数据管理策略。这种刚性与现代应用程序中复杂的访问模式不相吻合，如何及时有效地向大量核提供数据已经成为一项挑战。在这个项目中，我们研究了一种在未来的多核和多核架构上管理内存层次结构的软硬件集成方法。我们的论点是，灵活的存储层次结构为调整存储组织提供了基本的原语，将有助于软件使存储系统适应计算。软件将指定对硬件的提示，例如(1)将数据放置在哪里，这将利用数据的局部性并简化对数据的访问，以及(2)将哪些数据保留在芯片上以及如何共享芯片上的存储，这将提高芯片上存储的整体效率。我们工作的驱动应用程序将来自多种来源，包括与大学(和外部)同事在人工智能、生物信息学、计算机视觉、数据挖掘、事务内存和商业服务器工作负载方面的合作。这项拟议的研究开发了提高多核芯片利用率的关键技术。高效的多核芯片将使软件行业能够继续开发跨越商业、科学、国家安全和医疗保健的应用程序。

Multicore chips dominate the computing spectrum, replacing uniprocessors throughout the desktop, server, and mobile markets. In the future, manufacturers promise to deliver manycore chips which integrate 100s of diverse compute processors. An on-chip memory hierarchy needs to be carefully designed to ensure that the compute units are kept busy. Current memory hierarchies are hardware-managed with fixed policies for data management. This rigidity doesn't dovetail with the complex access patterns in modern applications and it has become challenging to effectively supply data to the large number of cores in a timely manner.In this project, we investigate an integrated hardware-software approach to managing the memoryhierarchy on future multicore and manycore architectures. Our thesis is that a flexible memoryhierarchy that provides basic primitives to the tune the storage organization will facilitate software to adapt memory system to the computation. Software will specify hints to hardware, such as (1) where toplace the data, which will exploit data locality and streamline the access to data and (2) what datato keep on-chip and how to share on-chip storage, which will improve the overall efficiency of on-chip storage.Driving applications for our work will be drawn from multiple sources, including collaborative efforts with university (and external) colleagues in artificial intelligence, bioinformatics, computer vision, data mining, transactional memory, and commercial server workloads. The proposed research develops technologies critical to improving the utility of manycore chips. Efficient manycore chips will enable the software industry to continue developing applications that span commerce, science, national security, and healthcare.