Design and Analysis of High Performance Cache-coherent Multiprocessors Based on Shared Buses

点击翻译按钮获取中文摘要

One of the most essential issues in a shared memory multiprocessor system isthe so called memory latency that includes both the main memory access timeand the interconnection network (IN) contention. The introduction of cachememory into parallel computers has been widely accepted as an efficient way ofimproving the system performance. However, multicaches create a cachecoherence problem which must be solved in order for a computer to workcorrectly. Traditional solution techniques for the cache coherence problem inshared memory multiprocessor systems have a potential bottleneck problem whichsignificantly restricted the scalability of multiprocessor systems. This pasresearch project investigates new distributed cache coherence protocols basedon high bandwidth, packet.switched multiple.bus INs. Two configurations ofthe multiple.bus will be considered in this research: hierarchicalstructures of buses and homogeneous single.level multiple buses. It alsoinvestigates analytical models for the cache protocols based on the twostructures to show the performance improvement of the new protocols. Theresearch thus involves (a) study of the correctness and efficiency of the newprotocols; (b) development of analytical models for the systems; (c)performance comparison of the two structures based on different applicationsoftwares; (d) examination of the effects of system parameters on the systemperformance including number of buses, cache block size, number of levels in ahierarchy, and number of modules connected to a bus at each level.