Design and Analysis of High Performance Cache-coherent Multiprocessors Based on Shared Buses

共享内存多处理器中最基本的问题之一 系统是所谓的内存延迟，包括两个主要的 存储器访问时间和互连网络（IN）争用。 的 在并行计算机中引入高速缓存已经被广泛地 被认为是提高系统性能的有效方法。 然而，多缓存会产生缓存一致性问题，这必须是 为了让计算机正常工作。 传统解决方案 共享内存中该高速缓存一致性问题的解决方法 多处理器系统具有潜在的瓶颈问题 这极大地限制了多处理器的可扩展性 系统. 这个pasresearch项目研究了新的分布式缓存 基于高带宽分组交换的一致性协议 多总线IN。多总线的两种配置将是 考虑在这项研究中：层次结构的巴士和 同构单级多总线。 它还调查了 基于这两种结构建立了该高速缓存协议的分析模型， 显示新协议的性能改进。 了研究 因此，涉及（a）研究的正确性和效率， （B）为系统开发分析模型; （c）两种结构的性能比较， 应用软件;（d）系统效果的检查 系统性能参数，包括总线数量、缓存 块大小、层次结构中的级别数和模块数 连接到每一级的总线。

One of the most essential issues in a shared memory multiprocessor system isthe so called memory latency that includes both the main memory access timeand the interconnection network (IN) contention. The introduction of cachememory into parallel computers has been widely accepted as an efficient way ofimproving the system performance. However, multicaches create a cachecoherence problem which must be solved in order for a computer to workcorrectly. Traditional solution techniques for the cache coherence problem inshared memory multiprocessor systems have a potential bottleneck problem whichsignificantly restricted the scalability of multiprocessor systems. This pasresearch project investigates new distributed cache coherence protocols basedon high bandwidth, packet.switched multiple.bus INs. Two configurations ofthe multiple.bus will be considered in this research: hierarchicalstructures of buses and homogeneous single.level multiple buses. It alsoinvestigates analytical models for the cache protocols based on the twostructures to show the performance improvement of the new protocols. Theresearch thus involves (a) study of the correctness and efficiency of the newprotocols; (b) development of analytical models for the systems; (c)performance comparison of the two structures based on different applicationsoftwares; (d) examination of the effects of system parameters on the systemperformance including number of buses, cache block size, number of levels in ahierarchy, and number of modules connected to a bus at each level.