Exploring the Design Space for High Performance and Low Cost Memory Hierarchies

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The main objective of this research is to investigate the issures related to hardware designs and performance evaluations of a number of innovative cache design techniques. These design techniques are currently being developed for single-chip general purpose processors and multiprocessors. Specifically, the focus of the research includes: 1) minimization of area cost of on-chip caches by CAT--caching address tags: 2) maximization of cache hit ratios by evenly distributing data across cache sets with the help of a few tag bits that change frequently during program executions; 3) investigation of potential impacts of the new CAT cache designs for various cache configurations as well as multiprocessor caches; and 4) devising analytical models, and performing trace-driven simulations and execution-driven simulations for evaluating implementation costs, performances, and design trade-offs of various designs.