Symbolic Simulation and Its Application to VLSI System Verification

符号仿真及其在VLSI系统验证中的应用

• 批准号: 8913667
• 负责人: Randal Bryant
• 金额: $ 33.85万
• 依托单位: Carnegie-Mellon University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1990
• 资助国家: 美国
• 起止时间: 1990-01-01 至 1993-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=8913667&HistoricalAwards=false
• 关键词: Symbolic; Simulation; Its; Application; VLSI

This research is on symbolic simulation as a basis for formally verifying complex IC designs. Symbolic simulation differs from classical simulation in that during simulator operation the user can set inputs not only to 0 or 1 but also to Boolean variables. The research exploits existing simulation technology by taking a behavioral approach to circuit verification. In this, the verifier applies logic simulation to compute the circuit's response to a series of stimuli chosen to detect all possible design errors. Research tasks include: selecting a set of simulation patterns which can defeat a malicious adversary attempting to foil the verifier; determining structures and algorithms, based on binary decision diagrams, for manipulating Boolean formulas; and investigating the use of the simulation system as an aid to debugging and design.

这项研究以符号仿真为基础，正式验证复杂的 IC 设计。 符号模拟与经典模拟的不同之处在于，在模拟器操作期间，用户不仅可以将输入设置为 0 或 1，还可以将输入设置为布尔变量。 该研究通过采用行为方法进行电路验证来利用现有的模拟技术。 在这种情况下，验证者应用逻辑仿真来计算电路对一系列激励的响应，这些激励被选择来检测所有可能的设计错误。 研究任务包括：选择一组模拟模式，可以击败试图挫败验证者的恶意对手；基于二元决策图确定用于操作布尔公式的结构和算法；并研究使用仿真系统来辅助调试和设计。