Research in Compiled Logic Simulation

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This research is on compiled simulation of IC designs. Topics explored are: (1) purely compiled methods for unit-delay and multi- delay simulation, (2) event-driven compiled simulation for multi- delay and nominal-delay simulation, and (3) hierarchal incremental compilation to reduce recompilation time. Existing techniques for purely compiled unit-delay simulation are being and extended to handle cyclic circuits. These techniques are also being used as a basis for creating a purely compiled multi-delay simulator. Techniques for zero-delay, event-driven, compiles simulation are being adapted to multi-delay and nominal-delay simulation. Finally, techniques for hierarchical compiled simulation are being extended to handle cyclic circuits, and are being adapted to perform compile-time partitioning of sub-circuits.