Research in Compiled Logic Simulation

编译逻辑仿真研究

• 批准号: 9006444
• 负责人: Peter Maurer
• 金额: $ 5.12万
• 依托单位: University of South Florida
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1990
• 资助国家: 美国
• 起止时间: 1990-07-15 至 1991-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9006444&HistoricalAwards=false
• 关键词: Research; Compiled; Logic; Simulation

This research is on compiled simulation of IC designs. Topics explored are: (1) purely compiled methods for unit-delay and multi- delay simulation, (2) event-driven compiled simulation for multi- delay and nominal-delay simulation, and (3) hierarchal incremental compilation to reduce recompilation time. Existing techniques for purely compiled unit-delay simulation are being and extended to handle cyclic circuits. These techniques are also being used as a basis for creating a purely compiled multi-delay simulator. Techniques for zero-delay, event-driven, compiles simulation are being adapted to multi-delay and nominal-delay simulation. Finally, techniques for hierarchical compiled simulation are being extended to handle cyclic circuits, and are being adapted to perform compile-time partitioning of sub-circuits.

本研究是对集成电路设计的编译仿真。探讨的主题有：(1)纯编译方法用于单位延迟和多延迟仿真，(2)事件驱动的多延迟和名义延迟仿真编译仿真，以及(3)分层增量编译以减少重新编译时间。现有的纯编译单元延迟仿真技术正在得到改进和扩展，以处理循环电路。这些技术也被用作创建纯编译的多延迟模拟器的基础。零延迟、事件驱动、编译仿真技术正适应于多延迟和名义延迟仿真。最后，层次编译模拟技术正在扩展到处理循环电路，并正在适应执行子电路的编译时划分。