Improving the Performance of Digital Logic Simulation

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This research is on compiled simulation of synchronous and asynchronous circuits. A digital logic simulation algorithm, called the Inversion Algorithm, is being investigated. This is a very efficient algorithm, yet capable of simulating any digital circuit. Basic extensions are being made to the algorithm. These involve including unit and multi-delay timing models, a logic model with unknown value, new gates, new types of functions, as well as bit-parallel simulation. Further, it is being redesigned so as to reduce both the complexity of the simulation and the number of events processed during simulation. Additional activities include extending the existing model to a multiple processor implementation, and to handle asynchronous sequential circuits. Application of the Inversion Algorithm to hierarchical simulation and incremental compilation is being explored.