Improving the Performance of Digital Logic Simulation

提高数字逻辑仿真的性能

• 批准号: 9403414
• 负责人: Peter Maurer
• 金额: $ 16.36万
• 依托单位: University of South Florida
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1994
• 资助国家: 美国
• 起止时间: 1994-08-01 至 1998-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9403414&HistoricalAwards=false
• 关键词: Improving; Performance; Digital; Logic; Simulation

This research is on compiled simulation of synchronous and asynchronous circuits. A digital logic simulation algorithm, called the Inversion Algorithm, is being investigated. This is a very efficient algorithm, yet capable of simulating any digital circuit. Basic extensions are being made to the algorithm. These involve including unit and multi-delay timing models, a logic model with unknown value, new gates, new types of functions, as well as bit-parallel simulation. Further, it is being redesigned so as to reduce both the complexity of the simulation and the number of events processed during simulation. Additional activities include extending the existing model to a multiple processor implementation, and to handle asynchronous sequential circuits. Application of the Inversion Algorithm to hierarchical simulation and incremental compilation is being explored.

本文主要研究同步和异步电路的编译仿真。一种数字逻辑仿真算法，称为反演算法，正在研究中。这是一个非常有效的算法，但能够模拟任何数字电路。该算法正在进行基本扩展。这些包括单元和多延迟定时模型，未知值逻辑模型，新门，新类型的函数，以及位并行仿真。此外，它正在重新设计，以减少仿真的复杂性和仿真期间处理的事件数量。其他活动包括将现有模型扩展到多处理器实现，以及处理异步顺序电路。研究了反演算法在分层仿真和增量编译中的应用。