RIA: Efficient Design of Fault-Tolerant Multiprocessors

结构容错（FT）多处理器的设计， 它可以围绕故障组件进行重新配置， 互连结构是计算机中一个重要问题 架构 虽然已经提出了许多设计方法， 以前，它们缺乏通用性，也失败了， 以解决实际问题，如低冗余、高效 可重构性和设计可扩展性。 在这个项目中，我们 主要涉及实现一个软件包， 节点覆盖和自守方法设计和 仿真容错系统，扩展两种设计方法 处理链路和交换机故障，设计技术， 快速和分布式重新配置， 更有效地实现我们的设计， 具有高平均情况容错性（因此具有高 可靠性成本比）。 我们还研究了节点- 覆盖公式可以应用于包含容错 在单处理器中，以及在各种逻辑电路中， 特别是那些可以实现为迭代阵列的 简单细胞

The design of structurally fault-tolerant (FT) multiprocessors, which can reconfigure around fault components to preserve interconnection structure, is an important problem in computer architecture. While a number of design methods have been proposed previously, they suffer from a lack of generality, and also fail to address practical issues like low redundancy, efficient reconfigurability and design scalability. In this project we are primarily concerned with implementing a software package based on the node-covering and automorphic methods for designing and simulating fault-tolerant systems, extending both design methods to deal with link and switch failures, devising techniques for very fast and distributed reconfiguration, developing principles for more efficient realizations of our designs, and designing systems with high average-case fault tolerance (and thus a high reliability-to-cost-ratio). We also investigate how the node- covering formulation can be applied to incorporate fault tolerance in uniprocessors, and in various types of logic circuits, especially those that can be realized as iterative arrays of simpler cells