RIA: Efficient Design of Fault-Tolerant Multiprocessors

结构容错多处理器的设计是计算机体系结构中的一个重要问题，它可以围绕故障部件进行重新配置以保持互连结构。虽然以前已经提出了一些设计方法，但它们缺乏通用性，也没有解决低冗余度、高效可重构性和设计可伸缩性等实际问题。在这个项目中，我们主要致力于实现一个基于节点覆盖和自同构方法的软件包，用于设计和模拟容错系统，扩展这两种设计方法以处理链路和交换机故障，设计非常快速和分布式的重新配置技术，开发更有效地实现我们的设计的原则，以及设计具有高平均容错能力(因此具有高可靠性成本比)的系统。我们还研究了如何将节点覆盖公式应用于单处理器和各种类型的逻辑电路中的容错，特别是那些可以实现为更简单单元的迭代阵列的逻辑电路

The design of structurally fault-tolerant (FT) multiprocessors, which can reconfigure around fault components to preserve interconnection structure, is an important problem in computer architecture. While a number of design methods have been proposed previously, they suffer from a lack of generality, and also fail to address practical issues like low redundancy, efficient reconfigurability and design scalability. In this project we are primarily concerned with implementing a software package based on the node-covering and automorphic methods for designing and simulating fault-tolerant systems, extending both design methods to deal with link and switch failures, devising techniques for very fast and distributed reconfiguration, developing principles for more efficient realizations of our designs, and designing systems with high average-case fault tolerance (and thus a high reliability-to-cost-ratio). We also investigate how the node- covering formulation can be applied to incorporate fault tolerance in uniprocessors, and in various types of logic circuits, especially those that can be realized as iterative arrays of simpler cells