CAREER: Algorithm-Hardware Co-design of Efficient Large Graph Machine Learning for Electronic Design Automation

职业：用于电子设计自动化的高效大图机器学习的算法-硬件协同设计

• 批准号: 2340273
• 负责人: Caiwen Ding
• 金额: $ 56.07万
• 依托单位: University of Connecticut
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2024
• 资助国家: 美国
• 起止时间: 2024-05-01 至 2029-04-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2340273&HistoricalAwards=false
• 关键词: CAREER; Algorithm; Hardware; Co; design

Estimating Power, Performance, and Area (PPA) earlier in the electronic design automation (EDA) flow would improve the Quality of Results (QoR) and reliability in chip design. The classical analytical or heuristic methods can be challenging to fine-tune, especially for complex problems. Machine learning (ML) methods have proven to be effective in addressing these problems. Graph Neural Networks (GNNs) have gained popularity since they are among the most natural ways to represent the fundamental objects in the EDA flow. However, with increased design complexity and chip capacity, an increasing performance gap exists between the extremely large graphs in EDA and the insufficient support from general-purpose hardware, such as mainstream graphics processing units (GPUs). This project aims to expedite the large graph machine learning on various EDA tasks, through a full-fledged development of efficient and scalable computing paradigms. This project's novelties are EDA domain knowledge-aware graph machine learning, training acceleration, and algorithm-hardware co-design and optimization. The project's broader significance and importance include: (1) to advance the field of machine learning in chip design, highlighted in National Artificial Intelligence Initiative; (2) to deepen the understanding of interactions among EDA domain knowledge, graph learning, and GPU acceleration; (3) to enrich the computer engineering curriculum and promote participation from undergraduates, underrepresented groups, and K-12 students in STEM fields through relevant programs.The project will develop a design paradigm for efficient, scalable and practical algorithm-hardware co-optimized solutions to significantly accelerate large graph machine learning on EDA tasks using a single GPU. This project consists of three coherent research thrusts: (1) to develop an algorithm-hardware co-optimized paradigm, focusing on restudying EDA graph features, introducing partitioning and selective re-growth methods, and tailoring GPU kernels for unified graph machine learning on EDA tasks using a single GPU; (2) to speed up single GPU for large circuit Graph Neural Network (GNN) training by implementing a tiled reversible architecture for low-memory training, and designing a maxK nonlinearity function to reduce computation costs; (3) to jointly integrate EDA domain knowledge, graph learning, and hardware optimizations to co-search for the appropriate hardware primitives and GNN compression strategies, as well as closely leverage the unique properties of circuit graphs.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

在电子设计自动化（EDA）流程中更早地估计功耗、性能和面积（PPA）将提高芯片设计的结果质量（QoR）和可靠性。经典的分析或启发式方法可能很难进行微调，特别是对于复杂的问题。机器学习（ML）方法已被证明可以有效地解决这些问题。图神经网络（GNN）已经越来越受欢迎，因为它们是表示EDA流程中基本对象的最自然的方法之一。然而，随着设计复杂性和芯片容量的增加，EDA中的超大图形与通用硬件（如主流图形处理单元（GPU））的支持不足之间存在越来越大的性能差距。该项目旨在通过全面开发高效和可扩展的计算范式，加快各种EDA任务的大型图机器学习。该项目的创新之处在于EDA领域知识感知图机器学习、训练加速以及算法硬件协同设计和优化。该项目更广泛的意义和重要性包括：（1）推进国家人工智能计划中强调的芯片设计中的机器学习领域;（2）加深对EDA领域知识，图学习和GPU加速之间相互作用的理解;（3）丰富计算机工程课程并促进本科生、代表性不足的群体，该项目将开发一种设计范式，用于高效，可扩展和实用的算法-硬件协同优化解决方案，以使用单个GPU显著加速EDA任务的大型图机器学习。该项目由三个连贯的研究重点组成：（1）开发算法-硬件协同优化范式，重点重新研究EDA图特征，引入分区和选择性重新生长方法，并定制GPU内核，用于EDA任务的统一图机器学习使用单个GPU;（2）通过实现用于低存储器训练的平铺可逆架构来加速用于大电路图神经网络（GNN）训练的单个GPU，设计maxK非线性函数以降低计算成本;（3）联合集成EDA领域知识、图学习和硬件优化，以共同搜索适当的硬件原语和GNN压缩策略，该奖项反映了NSF的法定使命，并被认为值得通过使用基金会的智力价值和更广泛的影响审查标准。