RIA: Comprehensive BIST Methodology for Delay and Stuck-at Faults

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This research is on developing efficient Built-In-Self-Test (BIST) schemes which detect delay as well as stuck at faults. Goals are reasonable testing time and minimal BIST hardware. The research has two thrusts. First is exploration of two weighted test pattern generator designs. Quaternary weighted test pattern generators, are being designed to be a good source of pseudo-random tests. Another is an algorithm to generate temporally correlated test patterns in such a way that the two vectors required to detect delay faults are best. The key idea is that the weights are used to generate correlations between consecutive vectors. Second, extensive fault simulations are being performed to develop an error model for the test pattern generators, as well as a composite fault model. Analysis is being made to determine temporal correlation between errors due to consecutive vectors, and distribution of errors in space. Compression schemes based on this data are planned.