ITR: A Completely Integrated Processor-Memory-Interconnect Architecture for Data Intensive Applications

点击翻译按钮获取中文摘要

A new, completely-integrated processor-memory-interconnect (CI-PMI)architecture model suitable for a range of data-intensiveapplications is proposed. Compared to the existing processor-in-memory(PIM) architectures, the proposed CI-PMI approach integrates morecompletely the processing, memory, and interconnect. This is achievedby starting with the classical architecture of high capacity memory,namely, a binary tree of decoders with memory modules as leaves, laidout as an H-tree. In the proposed model, copies of one or more typesof application-specific computing elements are added at differentlevels of the memory decoder tree, desired functionality added to thememory decoders to augment their role as interconnects as well as tosupport desired computation, and, if necessary, additional interconnectsadded between the application-specific processors, the memory modules,and the decoders. The proposed architecture will be developed anddemonstrated for a data-intensive application, namely motion estimationfor MPEG encoding.The results of the proposed research will be used to augment oneadvanced class, to be taught at USC as well as UCI. The class willtake a top-down view of advanced processor-in-memory architecturesincluding those developed in this project.The proposed research will advance the state of the art in computerarchitecture, VLSI, and VLSI CAD, leading to faster and cheaper designsfor day to day computation and information retrieval, exchange, andmanagement.