SHF:Small:New models, design, and test methods for long-term aging of nanometer VLSI

SHF：Small：纳米VLSI长期老化的新模型、设计和测试方法

• 批准号: 1719047
• 负责人: Sandeep Gupta
• 金额: $ 44万
• 依托单位: University of Southern California
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2017
• 资助国家: 美国
• 起止时间: 2017-08-15 至 2023-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1719047&HistoricalAwards=false
• 关键词: SHF; Small; New; models; design

Transistor aging refers to the phenomenon that a transistor degrades with use over time. Hence, as digital chips are used, transistor aging reduces their performance and increases power consumption. Aging also causes some chips to fail prematurely during their expected lifetimes (called lifetime failures). Since such failures can corrupt user data, cause expensive system downtime, and require expensive maintenance, industry practice requires lifetime failure rates to be of the order of 10 to 100 parts per million. This project will develop completely new methods and CAD tools for design and testing of digital chips to combat aging in uniquely efficient ways. These new methods and tools will dramatically improve yield, dramatically reduce power, and provide chips with extremely low lifetime failure rates, even as aging continues to grow in severity as we approach the end of Moore's Law. In turn, the society at large will reap significant benefits of this research, since lower cost digital systems with low lifetime failure rates will help improve many essential services, especially health, security, and finance. In addition, this project will train students and industry experts in the art and science of aging and its mitigation and prepare them for the era near and beyond the end of Moore's Law. Also, significant outreach effort will ensure that undergraduate students and students from groups underrepresented in STEM will participate in this research.This project has identified and will address three major limitations of existing aging research: serious inaccuracies of existing models in estimating long-term aging for real-life chip usage, the inability of existing memory designs to combat the most common type of memory aging, namely asymmetric aging, and the fact that existing approaches for post fabrication chip testing either provide extremely low yields or unacceptability high lifetime failure rates due to aging. Specifically, this project will develop completely new methods and tools for aging, demonstrate their effectiveness via extensive simulation studies and experiments on test chips, disseminate results and share new tools with academic and industry experts, and train students.

晶体管老化是指晶体管随着使用时间的推移而退化的现象。因此，随着数字芯片的使用，晶体管老化降低了它们的性能并增加了功耗。老化还会导致一些芯片在预期寿命内过早失效（称为寿命失效）。由于这样的故障可能破坏用户数据，导致昂贵的系统停机时间，并需要昂贵的维护，行业实践要求寿命故障率为百万分之10到100的量级。该项目将开发用于数字芯片设计和测试的全新方法和CAD工具，以独特有效的方式对抗老化。这些新的方法和工具将大大提高产量，大大降低功耗，并提供极低的寿命故障率的芯片，即使老化继续增长的严重性，因为我们接近年底的摩尔定律。反过来，整个社会将从这项研究中获益匪浅，因为低成本、低寿命故障率的数字系统将有助于改善许多基本服务，特别是健康、安全和金融。此外，该项目将培训学生和行业专家在艺术和科学的老化及其缓解，并准备他们的时代接近和超越摩尔定律的结束。此外，显著的推广工作将确保本科生和STEM中代表性不足的群体的学生将参与这项研究。该项目已经确定并将解决现有老龄化研究的三个主要局限性：现有模型在估计实际芯片使用的长期老化时的严重不准确性，现有存储器设计不能对抗最常见类型的存储器老化，即不对称老化，以及现有的用于制造后芯片测试的方法要么提供极低的成品率，要么由于老化而提供不可接受的高寿命故障率。具体而言，该项目将开发全新的老化方法和工具，通过广泛的模拟研究和测试芯片上的实验来证明其有效性，传播结果并与学术和行业专家分享新工具，并培训学生。

项目成果

Aging-resilient SRAM design: an end-to-end framework

• DOI: 10.1109/vts48691.2020.9107571
• 发表时间: 2020-04
• 期刊: 2020 IEEE 38th VLSI Test Symposium (VTS)
• 作者: X. Zuo;S. Gupta

Asymmetric sizing: An effective design approach for SRAM cells against BTI aging

不对称尺寸：SRAM 单元抗 BTI 老化的有效设计方法

• 发表时间: 2017
• 期刊: 2017 IEEE 35th VLSI Test Symposium (VTS
• 作者: Zuo, Xuan;Gupta, Sandeep
• 通讯作者: Gupta, Sandeep

Memristor-Specific Failures: New Verification Methods and Emerging Test Problems

• DOI: 10.1109/vts52500.2021.9794274
• 发表时间: 2022-04
• 期刊: 2022 IEEE 40th VLSI Test Symposium (VTS)
• 作者: B. Biswas;S. Gupta

HW-BCP: A Custom Hardware Accelerator for SAT Suitable for Single Chip Implementation for Large Benchmarks

HW-BCP：适用于大型基准的单芯片实施的 SAT 定制硬件加速器

• DOI: 10.1145/3394885.3431413
• 发表时间: 2021
• 期刊: 26th Asia and South Pacific Design Automation Conference (ASPDAC
• 作者: Park, Soowang;Nam, Jae-Won;Gupta, Sandeep K.
• 通讯作者: Gupta, Sandeep K.

Cache Design for Yield-per-Area Maximization: Switchable Spare Columns with Disabling (SSC-Disable)

• DOI: 10.1109/vts.2019.8758652
• 发表时间: 2019-04
• 期刊: 2019 IEEE 37th VLSI Test Symposium (VTS)
• 作者: Soowang Park;S. Gupta