SHF:Small:New models, design, and test methods for long-term aging of nanometer VLSI

晶体管老化是指晶体管随着使用时间的推移而退化的现象。因此，随着数字芯片的使用，晶体管老化会降低其性能并增加功耗。老化还会导致一些芯片在其预期寿命内过早失效(称为寿命故障)。由于此类故障会损坏用户数据，导致昂贵的系统停机时间，并且需要昂贵的维护费用，因此行业实践要求终生故障率在百万分之10到100的数量级。该项目将为数字芯片的设计和测试开发全新的方法和CAD工具，以独特有效的方式对抗老化。这些新的方法和工具将极大地提高产量，大幅降低功耗，并为芯片提供极低的寿命故障率，尽管随着摩尔定律接近尾声，老化的严重性仍在继续增长。反过来，整个社会将从这项研究中获得重大好处，因为低成本、低终生故障率的数字系统将有助于改善许多基本服务，特别是医疗、安全和金融。此外，该项目将培训学生和行业专家，了解衰老及其缓解的艺术和科学，并为摩尔定律即将结束和之后的时代做好准备。此外，重大的外展工作将确保本科生和来自STEM中代表性不足的群体的学生将参与这项研究。该项目已经确定并将解决现有老化研究的三个主要局限性：现有模型在估计实际芯片使用的长期老化方面存在严重不准确，现有存储器设计无法对抗最常见的存储器老化类型，即非对称老化，以及现有的制造后芯片测试方法要么提供极低的成品率，要么无法接受由于老化而导致的高终生失败率。具体地说，该项目将开发全新的老化方法和工具，通过广泛的模拟研究和测试芯片实验来展示其有效性，传播结果并与学术和行业专家共享新工具，以及培训学生。

Transistor aging refers to the phenomenon that a transistor degrades with use over time. Hence, as digital chips are used, transistor aging reduces their performance and increases power consumption. Aging also causes some chips to fail prematurely during their expected lifetimes (called lifetime failures). Since such failures can corrupt user data, cause expensive system downtime, and require expensive maintenance, industry practice requires lifetime failure rates to be of the order of 10 to 100 parts per million. This project will develop completely new methods and CAD tools for design and testing of digital chips to combat aging in uniquely efficient ways. These new methods and tools will dramatically improve yield, dramatically reduce power, and provide chips with extremely low lifetime failure rates, even as aging continues to grow in severity as we approach the end of Moore's Law. In turn, the society at large will reap significant benefits of this research, since lower cost digital systems with low lifetime failure rates will help improve many essential services, especially health, security, and finance. In addition, this project will train students and industry experts in the art and science of aging and its mitigation and prepare them for the era near and beyond the end of Moore's Law. Also, significant outreach effort will ensure that undergraduate students and students from groups underrepresented in STEM will participate in this research.This project has identified and will address three major limitations of existing aging research: serious inaccuracies of existing models in estimating long-term aging for real-life chip usage, the inability of existing memory designs to combat the most common type of memory aging, namely asymmetric aging, and the fact that existing approaches for post fabrication chip testing either provide extremely low yields or unacceptability high lifetime failure rates due to aging. Specifically, this project will develop completely new methods and tools for aging, demonstrate their effectiveness via extensive simulation studies and experiments on test chips, disseminate results and share new tools with academic and industry experts, and train students.