Efficient Techniques for High Quality Delay Testing of High-Speed Circuits

高速电路是高度流水线化的，使用锁存器而不是触发器，并采用大量的时间借用来减少流水线的开销。由于速度是一个关键的目标，高质量的延迟测试，如路径延迟测试，是必要的，这样的电路。使用锁存器和大量的时间借用有两个重要的后果，在延迟测试中引起新的问题。首先，由于一个块中的路径在其扇入和扇出中与块中的路径相互作用，因此有必要测试多块路径的延迟故障，即，穿过电路的多个块的路径。这种路径的数量往往是天文数字。其次，由于时间借用，锁存器输出端的值不是在任何固定时间应用，而是在一定范围内的某个时间应用。由于在锁存器的输出处施加值的确切时间从向量到向量以及从芯片的一个制造副本到另一个制造副本而变化，因此不可能设计模拟正常操作模式期间的事件的时序的可测试性设计（DFT）电路。提出了两种类型的测试应用方案，其可以使用扫描设计来实现，所述扫描设计在电路的正常操作期间不试图模仿事件的时序，而是在特定时钟边沿应用值并捕获响应。然后证明，它确实是可以使用这样的扫描，以精确地测试，路径延迟故障，基于锁存器的电路，使用时间借用。将开发使用上述DFT技术来有效地测试这种高速电路的技术。这将包括开发一种技术，以生成最佳的测试计划，以及工具，可以生成的测试类型，并执行所提出的方法所需的DFT电路的详细设计。拟议的研究将提供第一个系统的方法来实现，在合理的成本，有效的测试在高速电路中的路径延迟故障，同时提供可证明的高测试质量。开发的工具将用于教学目的并加以推广。

High-speed circuits are highly pipelined, use latches as opposed to flip-flops, and practice extensive time borrowing to reduce overheads of pipelining. Since speed is a critical objective, high quality delay testing, such as path delay testing, is imperative for such circuits. Use of latches and extensive time borrowing have two important consequences that give rise to new problems in delay testing. First, since the paths in one block interact with the paths in the blocks in its fan in and fan out, it becomes necessary to test for delay faults multi-block paths, i.e., paths that traverse multiple blocks of a circuit. The number of such paths is often astronomical. Second, due to time borrowing, values at a latch output are not applied at any fixed time, but at some time within a range. Since the exact time when values are applied at the outputs of a latch vary from vector to vector and from one fabricated copy of a chip to another, it is impossible to design design-for-testability (DFT) circuitry that mimics the timing of events during the normal mode of operation. Two types of test application schemes are proposed that can be implemented using scan designs that do not try to mimic the timing of events during the circuit's normal operation but apply values and capture responses at specific clock edges. It is then proven that it is indeed possible to use such scan to precisely test, for path delay faults, latch based circuits that use time borrowing. Techniques to use above DFT technique to efficiently test such high-speed circuits will be developed. This will include development of a technique to generate optimal test plans as well as tools that can generate the types of tests and perform detailed design of DFT circuitry required by the proposed approach. The proposed research will provide the first systematic approach for achieving, at reasonable costs, efficient testing for path delay faults in high speed circuits while providing provably high test quality. The tools developed will be leveraged and extended for instructional purposes.