Analog VLSI Neural Network Employing A Novel Linear Synapse

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This is SBIR Phase II research on designing a synapse for a neural network (NN). During Phase I the company devised a novel synapse circuit, which is linear over a range that is 10 times that of previous state-of-the-art circuits, and half the size of previous circuits. Also a NN for the chip was designed. During Phase II, the company is designing and testing the remaining network elements and improving the synapse. A full scale prototype chip that implements on-chip learning, and contains up to 650,000 synapses is being developed. The chip design enables interconnection of several chips in order to form a multi-layer network. In addition a prototype back propagation network which will integrate all network elements on a single chip and allows interconnection of at least two chips is being designed.