Analog CMOS Neural Circuits for Speech Recognition

用于语音识别的模拟 CMOS 神经电路

• 批准号: 9215536
• 负责人: John Tanner
• 金额: $ 24.99万
• 依托单位: Tanner Research Incorporated
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1993
• 资助国家: 美国
• 起止时间: 1993-03-15 至 1996-02-29
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9215536&HistoricalAwards=false
• 关键词: Analog; CMOS; Neural; Circuits; Speech

Real-time recognition of speaker-independent connected speech has proven to be a difficult problem for electronic systems. Low-precision highly parallel analog neural networks have been shown to recognize speaker-dependent small-vocabulary connected speech using standard components. This project will research and develop massively parallel custom integrated circuits that will perform this task, using integrated delay lines and analog computing networks. Phase I has included the design and fabrication of test chips to prove the feasibility of our development; the Phase II effort will continue this development through design, fabrication and testing of full- scale prototype systems. The approach utilizes standard readily available CMOS Bulk integrated circuit technology so products arising from this research can be fabricated reliably and economically by a number of vendors. Phase I culminated in the fabrication and testing of an expandable, programmable single-chip speech classifier. This chip operates at over 100 MIPS and enjoys a 50x improvement in performance over DSP chips (normalized to the same silicon area usage). The P.I. has also shown the feasibility of using floating-nodes to provide nonvolatile storage of analog voltages. These voltages can be used to control the operation of the chip thus implementing the capability to learn or be trained in the field. During Phase II, the P.I. will investigate the mapping of learning algorithms to efficient silicon circuits. This proposed research applies the P.I.'s experience to the challenging and important problem of real-time speech recognition and may lead directly to inexpensive products with wide commercial applicability.

非特定人连接语音的实时识别一直是电子系统面临的一个难题。低精度、高度并行的模拟神经网络已被证明能够使用标准分量识别依赖于说话人的小词汇量连接语音。该项目将研究和开发大规模并行定制集成电路，使用集成延迟线和模拟计算网络来执行这一任务。第一阶段包括测试芯片的设计和制造，以证明我们开发的可行性；第二阶段的工作将通过设计、制造和测试全尺寸原型系统来继续这一开发。该方法利用标准的现成的CMOS体集成电路技术，因此这项研究产生的产品可以由许多供应商可靠而经济地制造出来。第一阶段最终完成了可扩展、可编程的单芯片语音分类器的制造和测试。该芯片的运行速度超过100MIPS，性能比DSP芯片提高50倍(归一化为相同的硅片面积使用量)。P.I.还证明了使用浮动节点提供模拟电压的非易失性存储的可行性。这些电压可以用来控制芯片的操作，从而实现在现场学习或接受培训的能力。在第二阶段，P.I.将调查学习算法与高效硅电路的映射。这项研究将P.I.的S经验应用于实时语音识别这一具有挑战性的重要问题，并可能直接导致具有广泛商业适用性的廉价产品。