Analog CMOS Neural Circuits for Speech Recognition

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Real-time recognition of speaker-independent connected speech has proven to be a difficult problem for electronic systems. Low-precision highly parallel analog neural networks have been shown to recognize speaker-dependent small-vocabulary connected speech using standard components. This project will research and develop massively parallel custom integrated circuits that will perform this task, using integrated delay lines and analog computing networks. Phase I has included the design and fabrication of test chips to prove the feasibility of our development; the Phase II effort will continue this development through design, fabrication and testing of full- scale prototype systems. The approach utilizes standard readily available CMOS Bulk integrated circuit technology so products arising from this research can be fabricated reliably and economically by a number of vendors. Phase I culminated in the fabrication and testing of an expandable, programmable single-chip speech classifier. This chip operates at over 100 MIPS and enjoys a 50x improvement in performance over DSP chips (normalized to the same silicon area usage). The P.I. has also shown the feasibility of using floating-nodes to provide nonvolatile storage of analog voltages. These voltages can be used to control the operation of the chip thus implementing the capability to learn or be trained in the field. During Phase II, the P.I. will investigate the mapping of learning algorithms to efficient silicon circuits. This proposed research applies the P.I.'s experience to the challenging and important problem of real-time speech recognition and may lead directly to inexpensive products with wide commercial applicability.