SBIR Phase II: Integrated Multi-Track Giant Magneto- resistance Ratio Read/Write Heads with Integrated Circuitry

SBIR第二阶段：带有集成电路的集成多轨巨磁阻比读/写头

• 批准号: 9413349
• 负责人: Arthur Pohm
• 金额: $ 30万
• 依托单位: Nonvolatile Electronics Inc
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1995
• 资助国家: 美国
• 起止时间: 1995-10-01 至 1997-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9413349&HistoricalAwards=false
• 关键词: SBIR; Phase; II; Integrated; Multi

9413349 Pohm The SBIR Phase II project proposes several intermediate and long range research objectives to extend promising Phase I results obtained on multiple, giant magnetoresistance (GMR) read head sensors to the point where they can be applied commercially. These objectives are to explore low temperature glasses and other materials to form a smooth surface at the top of the first half gap material deposited over the lower shield, in order to optimize the GMR material. The use of cobalt-plantinum or other high coercivity materials at the edges of the sensors is to be explored for domain stabilization. In addition, both sensor structures with one magnetic layer pinned by exchange and structures without pinning are to be examined and compared. Read heads made with these GMR sensors are to be fabricated and evaluated on disks for signal output and noise. Modeling will also be extended to the combined longitudinal, end-on structures. Multiple folded head sensors are to be explored for use in longer range, extremely high density (1-5 billion bits/sq. in.), high performance (100 to 200 MHz), applications along with the required, optimized, integrated, SOS-CMOS or BiCMOS circuitry and connection channel. A commercialization plan was developed which includes a follow-on commitment by the world's largest thin film head producer.

9413349 Pohm SBIR第二阶段项目提出了几个中长期研究目标，以扩展在多个巨磁电阻(GMR)读取头传感器上获得的有希望的第一阶段成果，使其能够商业化应用。这些目标是探索低温玻璃和其他材料，以形成光滑的表面在第一半间隙材料沉积在下屏蔽层上，以优化巨磁电阻材料。在传感器的边缘使用钴植物或其他高矫直力材料将被探索以实现磁区稳定。此外，还对具有交换钉扎的一个磁层的传感器结构和没有钉扎的结构进行了检验和比较。用这些GMR传感器制造的读取头将在磁盘上制造并评估信号输出和噪声。建模还将扩展到组合的纵向、端接结构。多个折叠式磁头传感器将被探索用于更远距离、极高密度(10-50亿比特/平方英尺)。In.)、高性能(100至200 MHz)、应用以及所需的、优化的、集成的SOS-CMOS或BiCMOS电路和连接通道。制定了一项商业化计划，其中包括世界上最大的薄膜头部生产商的后续承诺。