Analytical Model of Superscalar Processor Performance

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Trace-driven simulators (TDS) are widely used by processor architects to accurately assess the expected performance of a processor design. While necessary and useful, TDS have some shortcomings. Traces of realistic programs are usually very large and expensive to store, and simulation of traces can very time consuming. Furthermore, simulation does not yield a characterization of the factors that determine performance, and hence can not recommend specific changes to enhance performance. The two-fold objectives of this research are (1) to investigate alternatives to TDS for accurately quantifying processor performance; and (2) to seek to characterize factors that determine superscalar processor performance. The effort will involve developing an analytical model of machine behavior, based on which processor performance can be computed without requiring tedious trace-driven simulation. It is hoped that the same analytical model, in addition to providing a useful tool, will also provide a characterization of superscalar processor performance. This characterization can potentially reveal fundamental laws governing processor performance that can be mathematically formulated. In this research project, processor performance is modeled as a composition of program parallelism and machine parallelism. Program parallelism is represented by two distribution functions that are derived from the execution trace of benchmark and captures the control and data dependencies in the program. This derivation is analogous to performing a type of transform on the execution trace from the time domain to the transformed domain. Consequently the two distribution functions can be viewed as concise spectral representation of the program parallelism. Machine parallelism represents the resources available in the processor for the concurrent processing of instructions. A machine is modelled as a network, or circuit, of primitive components, e.g. buffers and scalar pipelines. Macro models of the components and the model for their serial and parallel interconnections will be developed. With such a circuit of model microarchitectures, complex superscalar processors can be effectively and rigorously modeled. While the research appears somewhat theoretical in nature, a great deal of experimentation is required and expected. The plan is to work with realistic programs with extremely long traces as well as a wide range of state-of-the-art implementations of real instruction set architectures. The Alpha 21164 and the Power PC 620 designs and the SPEC92 Shen benchmark suites are used as the primary experimentation vehicles.