Delta Cache Coherence Protocols

找到一个好的缓存一致性问题的解决方案是有效使用中大规模多处理器的关键。在这类系统中，远程内存访问的高成本使进程能够本地访问数据变得重要，但允许进程保存共享可写数据的本地副本需要找到一种保持副本一致性的好方法。本项目将研究一系列新的高速缓存一致性协议，称为增量高速缓存协议，它们在几乎不同步或不同步的情况下保持高速缓存一致性。Delta缓存协议是目录协议，而不是Snoopy协议。增量缓存协议基于等距时间系统，即由一类称为等距网络的网络实现的时间系统。Isotach网络的特点不是拓扑--它们可以在任意拓扑上实现--而是它们提供了关于操作交付的相对顺序的保证。Isotach系统需要定制的交换元件，但可以使用现成的处理器构建，配置范围从紧密耦合的多处理器到工作站集群。对同位素系统的模拟研究表明，在现实的工作负荷下，它们的表现优于同类的传统系统，在许多情况下是一个数量级或更多。在极端情况下，它们的表现比传统系统高出任意数量。该项目对高速缓存一致性问题进行了为期三年的研究，目的是探索等距网络打开的高速缓存一致性协议的设计空间，并评估Delta高速缓存协议的性能。探索性工作包括协议和缓存设计；将该方法扩展到各种拓扑结构和存储层次的其他级别；以及设计方法来降低协议的网络带宽要求，并通过数据迁移提高协议的效率。性能研究将模拟具有缓存的等值缓存和传统系统，并比较它们在各种工作负载下的性能。模拟将建立在已完成的不带缓存的等值线系统模拟的基础上。

Finding a good solution to the cache coherence problem is critical to the effective use of medium and large scale multiprocessors. The high cost of remote memory access in such systems makes it important that processes be able to access data locally, but allowing processes to hold local copies of shared writable data requires finding a good way to keep the copies consistent. This project will investigate a new family of cache coherence protocols called delta cache protocols that maintain cache coherence with little or no synchronization. Delta cache protocols are directory, as opposed to snoopy, protocols. The delta cache protocols are based on isotach time systems, time systems implemented by a class of networks called isotach networks. Isotach networks are characterized not by topology - they can be imp lemented on arbitrary topologies - but by the guarantees they provide about the relative order in which operations appear to be delivered. Isotach systems require custom switching elements, but can be built with off- the-shelf processors and in a variety of configurations ranging from tightly -coupled multiprocessors to clusters of workstations. A simulation study of isotach systems shows that they outperform comparable conventional systems under realistic workloads, in many cases by an order of magnitude or more. In extreme cases, they outperform conventional systems by an arbitrary amount. The project is a three year study of the cache coherence problem with the goals of exploring the design space for cache coherence protocols opened by isotach networks; and evaluating the performance of delta cache protocols. The exploratory work includes protocol and cache design; extending the approach to a variety of topologies and to other levels of the memory hierarchy; and devising ways to reduce the network bandwidth requirements of the protocols and to improve the efficiency of the protocols through data migration. The performance study will simulate isotach and conventional systems with caches and compare their performance under a variety of workloads. The simulation will build on the already completed simulation of isotach systems without caches.