Delta Cache Coherence Protocols

解决该高速缓存的一致性问题是有效利用中、大规模多处理机的关键。 在这样的系统中，远程存储器访问的高成本使得进程能够本地访问数据变得重要，但是允许进程保持共享可写数据的本地副本需要找到一种好的方法来保持副本一致。 这个项目将研究一个新的高速缓存一致性协议家族，称为增量高速缓存协议，该协议在很少或没有同步的情况下保持高速缓存一致性。 增量缓存协议是目录协议，而不是窥探协议。增量缓存协议基于等速时间系统，该时间系统由一类称为等速网络的网络实现。 等速网络的特征不是拓扑结构--它们可以在任意拓扑结构上实现--而是它们提供的关于操作似乎被交付的相对顺序的保证。 等转速系统需要定制的开关元件，但可以用现成的处理器和从紧耦合的多处理器到工作站集群的各种配置来构建。 等速系统的模拟研究表明，它们在实际工作负载下的性能优于可比的传统系统，在许多情况下是一个数量级或更多。 在极端情况下，它们的性能比传统系统高出任意数量。 该项目是一项为期三年的该高速缓存一致性问题研究，目的是探索等速网络打开的高速缓存一致性协议的设计空间;以及 评估增量高速缓存协议的性能。 探索性的工作包括协议和高速缓存设计;扩展的方法，以各种拓扑结构和其他层次的内存层次结构;和设计的方法，以减少网络带宽的要求的协议，并通过数据迁移，以提高协议的效率。 性能研究将模拟isotach和传统的系统与缓存，并比较其性能下的各种工作负载。 该模拟将建立在已经完成的无缓存等速系统模拟的基础上。

Finding a good solution to the cache coherence problem is critical to the effective use of medium and large scale multiprocessors. The high cost of remote memory access in such systems makes it important that processes be able to access data locally, but allowing processes to hold local copies of shared writable data requires finding a good way to keep the copies consistent. This project will investigate a new family of cache coherence protocols called delta cache protocols that maintain cache coherence with little or no synchronization. Delta cache protocols are directory, as opposed to snoopy, protocols. The delta cache protocols are based on isotach time systems, time systems implemented by a class of networks called isotach networks. Isotach networks are characterized not by topology - they can be imp lemented on arbitrary topologies - but by the guarantees they provide about the relative order in which operations appear to be delivered. Isotach systems require custom switching elements, but can be built with off- the-shelf processors and in a variety of configurations ranging from tightly -coupled multiprocessors to clusters of workstations. A simulation study of isotach systems shows that they outperform comparable conventional systems under realistic workloads, in many cases by an order of magnitude or more. In extreme cases, they outperform conventional systems by an arbitrary amount. The project is a three year study of the cache coherence problem with the goals of exploring the design space for cache coherence protocols opened by isotach networks; and evaluating the performance of delta cache protocols. The exploratory work includes protocol and cache design; extending the approach to a variety of topologies and to other levels of the memory hierarchy; and devising ways to reduce the network bandwidth requirements of the protocols and to improve the efficiency of the protocols through data migration. The performance study will simulate isotach and conventional systems with caches and compare their performance under a variety of workloads. The simulation will build on the already completed simulation of isotach systems without caches.