Prototyping Multiscalar Processors

这个项目正在评估一种新的体系结构范例，它可以提取和利用顺序代码中的并行性。这种新方法既使用编译器中的软件调度(如在VLIW中)，又使用运行时的硬件调度(如在超标量体系结构中)。编译器将代码分割成大的指令块，这些指令块形成控制流图的子图，但不一定是基本块。编译器将同步信息追加到每个块，以描述哪些寄存器必须与块共享。编译器将同步信息附加到描述哪些寄存器必须与其他块共享的每个块。块或任务被传递到独立的相同并行执行单元，每个并行执行单元顺序执行其任务。任务的调度是乐观的，因此当一些任务不会在顺序系统中执行时，它们可能会由一个单元执行；在这种情况下，任务被“挤压”，这意味着它们的结果不会写入内存或寄存器。在每个任务结束时，它会一直阻塞，直到系统确定该任务不会被挤压；此时提交结果。执行单元的集合在逻辑上看起来是具有单个寄存器堆的一个单元。共享寄存器值在执行单元间网络上传递，需要共享值的任务阻塞，直到产生值。在该奖项的前两年，该奖项致力于新体系结构的编译器设计，使用模拟与其他体系结构进行比较，以及体系结构的概念改进。在以后的几年里，预计工作的重点将是执行。

This project is evaluating a new architectural paradigm that can extract and exploit the parallelism in sequential code. This new approach uses both software scheduling in the compiler, as in VLIW, and hardware scheduling at run-time, as in superscalar architectures. The compiler segments code into large blocks of instructions that form subgraphs of the control-flow graph, though not necessarily basic blocks. The compiler appends synchronization information to each block that describes which registers must be shared with blocks. The compiler appends synchronization information to each block that describes which registers must be shared with other blocks. The blocks or tasks are passed to separate identical parallel execution units, each of which executes its task sequentially. Tasks are scheduled optimistically, so that some tasks may be executed by a unit when they would not be executed in a sequential system; in such cases, the tasks are "squashed," which means that their results are not written to memory or registers. At the end of each task, it blocks until the system determines that the task will not be squashed; at that time results are committed. The collection of execution units appears logically to be one unit, with a single register file. Shared register values are passed on an inter-execution-unit network, and tasks that need shared values block until the values are produced. During the first two years of this award is devoted to compiler design for the new architecture, to comparison with other architectures using simulation, and to conceptual refinement of the architecture. During later years, work is expected to focus on implementation.