Prototyping Multiscalar Processors

多标量处理器原型设计

• 批准号: 9505853
• 负责人: Gurindar Sohi
• 金额: $ 130.85万
• 依托单位: University of Wisconsin-Madison
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1995
• 资助国家: 美国
• 起止时间: 1995-08-01 至 2000-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9505853&HistoricalAwards=false
• 关键词: Prototyping; Multiscalar; Processors

This project is evaluating a new architectural paradigm that can extract and exploit the parallelism in sequential code. This new approach uses both software scheduling in the compiler, as in VLIW, and hardware scheduling at run-time, as in superscalar architectures. The compiler segments code into large blocks of instructions that form subgraphs of the control-flow graph, though not necessarily basic blocks. The compiler appends synchronization information to each block that describes which registers must be shared with blocks. The compiler appends synchronization information to each block that describes which registers must be shared with other blocks. The blocks or tasks are passed to separate identical parallel execution units, each of which executes its task sequentially. Tasks are scheduled optimistically, so that some tasks may be executed by a unit when they would not be executed in a sequential system; in such cases, the tasks are "squashed," which means that their results are not written to memory or registers. At the end of each task, it blocks until the system determines that the task will not be squashed; at that time results are committed. The collection of execution units appears logically to be one unit, with a single register file. Shared register values are passed on an inter-execution-unit network, and tasks that need shared values block until the values are produced. During the first two years of this award is devoted to compiler design for the new architecture, to comparison with other architectures using simulation, and to conceptual refinement of the architecture. During later years, work is expected to focus on implementation.

这个项目正在评估一个新的架构范例，可以提取和利用顺序代码中的并行性。 这种新的方法使用两个软件调度在编译器中，如在VLIW中，和硬件调度在运行时，如在超标量体系结构。 编译器将代码分割成大的指令块，这些指令块形成控制流图的子图，但不一定是基本块。 编译器将同步信息附加到每个块，这些信息描述哪些寄存器必须与块共享。 编译器将同步信息附加到每个块，这些信息描述哪些寄存器必须与其他块共享。 块或任务被传递到单独的相同的并行执行单元，每个并行执行单元顺序地执行其任务。 任务被乐观地调度，使得一些任务可以由一个单元执行，而它们在顺序系统中不会被执行;在这种情况下，任务被“压扁”，这意味着它们的结果不会被写入内存或寄存器。 在每个任务结束时，它会阻塞，直到系统确定该任务不会被压缩;此时，结果将被提交。 执行单元的集合在逻辑上看起来是一个单元，具有单个寄存器文件。 共享寄存器值在执行单元间的网络上传递，需要共享值的任务会阻塞，直到生成这些值。 该奖项的前两年致力于新架构的编译器设计，与其他使用模拟的架构进行比较，并对架构进行概念上的改进。 今后几年的工作预计将侧重于执行。