Studies in Instruction-Level Parallel Processing

指令级并行处理研究

• 批准号: 9303030
• 负责人: Gurindar Sohi
• 金额: $ 37.58万
• 依托单位: University of Wisconsin-Madison
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1993
• 资助国家: 美国
• 起止时间: 1993-08-01 至 1997-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9303030&HistoricalAwards=false
• 关键词: Studies; Instruction; Level; Parallel; Processing

This research investigates instruction-level parallel (ILP) processors. The goal is to develop processors that can sustain over 10 instructions per cycle when executing arbitrary non-numeric applications such as compilers, simulators, CAD, text processing, and database programs. The research builds on the previous studies of ILP to expand the foundation for ILP processors. A novel paradigm for ILP processors, the multiscalar processing paradigm, continues to be developed, with the goal of bringing the multiscalar paradigm into the mainstream of processor design. Issues relevant to the operation of a multiscalar processor such as data memory systems, instruction memory systems, inter-operation communication mechanisms, and task specification and execution, are studied using detailed simulation models. Also investigated is software support for multiscalar processors.

这项研究调查了指令级并行 (ILP) 处理器。 目标是开发在执行编译器、模拟器、CAD、文本处理和数据库程序等任意非数字应用程序时，每个周期能够支持 10 条以上指令的处理器。 该研究建立在先前 ILP 研究的基础上，扩展了 ILP 处理器的基础。 ILP 处理器的一种新颖范式，即多标量处理范式，正在继续开发，其目标是将多标量范式带入处理器设计的主流。 使用详细的仿真模型研究与多标量处理器的操作相关的问题，例如数据存储系统、指令存储系统、操作间通信机制以及任务规范和执行。 还研究了对多标量处理器的软件支持。