Innovations in Resource Organization and Use in Multicore Processors

该项目研究在组织和使用未来多核处理器的计算和存储资源方面的创新。这些创新对于保持微处理器性能的增长至关重要，微处理器性能是计算机产业的驱动力。我们将研究两个具体的创新方向：(I)在多核内新颖而高效地组织和使用计算资源；(Ii)在多核内新颖而高效地组织和使用高速缓存资源。第一个研究方向使用一个新提出的框架，计算重新分配，它将计算片段转移到最合适的资源上执行，对更高级别的软件是透明的。所提出的技术有可能极大地提高多核处理器的计算资源执行程序的效率，从而导致更好的性能、更好的功率效率、更好的可靠性和更好的热管理。第二个研究方向是研究协同缓存，这是最近提出的一种通过单个缓存之间的合作来构建聚合的、全局管理的缓存的建议。合作缓存的研究将包括创新的合作策略，以协调多核处理器的组合缓存资源，以实现三个同时目标：(1)减少内存访问延迟，(2)提高吞吐量、公平性和服务质量，(3)多核缓存的性能和功耗管理。研究方法广泛使用全系统、循环级模拟器进行模拟。该项目使用了各种各样的基准程序，包括标准基准测试套件以及其他程序，包括商业工作负载，这些程序以多种不同的编程语言编写，并在多种商业操作系统上运行。模拟能力包括可以量化各种形式的效率的模型，包括功率和面积模型。预计这项研究将在几个方面产生更广泛的影响，包括研究生的培训、对商业计算机设计的影响、增强用于设计强大计算机的知识体系，以及开发有助于培养未来计算机科学家和工程师的教学工具。

This project investigates innovations in the organization and use of computation and storage resources for future multicore processors. Such innovations are critical to maintaining growth in microprocessor performance, which is the driver of the computer industry.Two specific directions for innovation will be investigated: (i) novel and efficient organization and use of computation resources within a multicore, and (ii) novel and efficient organization and use of cache resources within a multicore. The first research direction uses a newly proposed framework, Computation Reassignment, which transfers computation fragments to the most appropriate resources for execution,transparent to the higher level software. The proposed technique has the potential to greatly increase the efficiency with which the computation resources of a multicore processor execute a program, which can lead to better performance, better power efficiency, better reliability, and better thermal management. The second research direction investigates Cooperative Caching, a recent proposal for constructing an aggregate,globally managed cache via cooperation between the individual caches. The investigation of cooperative caching will include innovative cooperation policies to coordinate the combined cache resources of a multicore processor to achieve three simultaneous goals: (1) memory access latency reduction, (2) throughput, fairness and quality of service improvement and (3) performance and power management of multicore caches. The research methodology makes extensive use of simulations using full-system, cycle-level simulators. The project uses a wide variety of benchmark programs including standard benchmark suites as well as otherprograms, including commercial workloads, written in a number of different programming languages and run on multiple, commercial operating systems. The simulation capabilities include models that allow a quantification of various forms of efficiency, including power and area models.The research is expected to have a broader impact in several ways, including the training of graduate students, impact on commercial computer designs, enhancing the body of knowledge used to design powerful computers, as well as the development of pedagogical tools that will be useful in educating future computer scientists and engineers.