VLSI Delay Vernier Architectures and Applications

VLSI 延迟游标架构和应用

• 批准号: 9531729
• 负责人: Wentai Liu
• 金额: $ 21.43万
• 依托单位: North Carolina State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1996
• 资助国家: 美国
• 起止时间: 1996-06-01 至 2000-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9531729&HistoricalAwards=false
• 关键词: VLSI; Delay; Vernier; Architectures; Applications

This project is concerned with two performance enhancing techniques of VLSI systems that have developed from wave pipelining: delay vernier architectures and non-zero skew design methodologies. Many high performance applications require extremely fine timing resolution or very high data sampling rates. Examples include high speed network transceivers, A/D converters, phase-locked and delay- locked and delay-locked loops, and ATE pin electronics. Normally, expensive circuit technologies and very high frequency clock signals are used to satisfy these performance requirements. However, the proposed delay vernier structures are capable of achieving a very high time resolution using CMOS technologies and relatively slow clock signals. This research will focus on refining and extending delay vernier architectures and design techniques so that their usefulness is maximized. The effectiveness of the architecture in a number of applications will be evaluated. Also, some real-world factors, such as process variation and noise, will be investigated. The non-zero skew design approach allows the VLSI systems designer to take advantage of intentional skew to optimize clock distribution for a particular set of propagation delays, and thereby greatly improve system throughput. A critical necessity for these systems in the ability to create precise clock skews. This research will focus very strongly on the delay vernier technique, since it can provide this required ability. Finally, prototypes systems will be built for several promising applications.

本计画主要探讨两种从波管线发展而来的超大规模积体电路系统效能提升技术：延迟游标架构与非零偏斜设计方法。 许多高性能应用需要极高的时序分辨率或极高的数据采样率。 示例包括高速网络收发器、A/D转换器、锁相环和延迟锁定环路以及ATE引脚电子器件。 通常，使用昂贵的电路技术和非常高频率的时钟信号来满足这些性能要求。 然而，所提出的延迟游标结构能够使用CMOS技术和相对慢的时钟信号来实现非常高的时间分辨率。 这项研究将集中在细化和扩展延迟游标架构和设计技术，使其效用最大化。 将评估该架构在一些应用程序中的有效性。 此外，一些现实世界的因素，如过程变化和噪声，将进行调查。 非零偏斜设计方法允许VLSI系统设计者利用有意偏斜来优化针对特定传播延迟集合的时钟分布，从而极大地提高系统吞吐量。 这些系统的一个关键必要条件是能够创建精确的时钟偏差。 这项研究将非常强烈地集中在延迟游标技术，因为它可以提供这种所需的能力。 最后，原型系统将建立几个有前途的应用。