VLSI Delay Vernier Architectures and Applications

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This project is concerned with two performance enhancing techniques of VLSI systems that have developed from wave pipelining: delay vernier architectures and non-zero skew design methodologies. Many high performance applications require extremely fine timing resolution or very high data sampling rates. Examples include high speed network transceivers, A/D converters, phase-locked and delay- locked and delay-locked loops, and ATE pin electronics. Normally, expensive circuit technologies and very high frequency clock signals are used to satisfy these performance requirements. However, the proposed delay vernier structures are capable of achieving a very high time resolution using CMOS technologies and relatively slow clock signals. This research will focus on refining and extending delay vernier architectures and design techniques so that their usefulness is maximized. The effectiveness of the architecture in a number of applications will be evaluated. Also, some real-world factors, such as process variation and noise, will be investigated. The non-zero skew design approach allows the VLSI systems designer to take advantage of intentional skew to optimize clock distribution for a particular set of propagation delays, and thereby greatly improve system throughput. A critical necessity for these systems in the ability to create precise clock skews. This research will focus very strongly on the delay vernier technique, since it can provide this required ability. Finally, prototypes systems will be built for several promising applications.