CMOS IC Performance Enhancement Via Wave Pipelining

刘波流水线技术有很好的潜力来提高数字系统设计的性能。要成功实现CMOSWAVE流水线，需要一种紧密结合技术、工艺、电路、逻辑和系统架构设计知识的设计方法，以及用于设计和测试的CAD工具。虽然初步的结果已经清楚地证明了在CMOS波流水线的可行性，但在有效地设计波流水线系统方面还需要做更多的工作。本项目旨在开发和演示基于CMOS工艺的波浪流水线的设计技术和VLSI结构，主要是因为它具有广泛的可获得性和相对较低的成本。高速系统中波形流水线的有用应用领域包括高速采样电路、数字锁相环、多路复用器和解复用器、纠错电路、光纤数据和时钟恢复。

Liu Wave pipelining techniques have a good potential to improve the performance of a digital system design. The success of achieving CMOS wave pipelining requires a design methodology which tightly couples the knowledge of technology, process, circuit, logic, and system architecture design as well as CAD tools for design and testing. While preliminary results have clearly demonstrated the feasibility of wave pipelining in CMOS, more work is needed toward the efficient design of wave pipelined systems. This project is to develop and demonstrate design techniques and VLSI structures for wave pipelining based on CMOS technology, primarily because of its wide availability and relatively low cost. Useful application areas for wave pipelining in high speed systems include high speed sampling circuitry, digital phase locked loops, MUX and DEMUX, error correction circuits, data and clock recovery for fiber optics.