Current Mode Band-Limited Signaling for Deep Submicron Global Interconnects

用于深亚微米全球互连的电流模式带限信令

• 批准号: 0200063
• 负责人: Wentai Liu
• 金额: $ 15万
• 依托单位: North Carolina State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2002
• 资助国家: 美国
• 起止时间: 2002-07-15 至 2005-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0200063&HistoricalAwards=false
• 关键词: Current; Mode; Band; Limited; Signaling

Recent trends in submicron CMOS scaling suggest that global interconnects will increasingly become a major performance limitation due to increased signal delay and cross-talk noise. The implementation of copper and low k wiring technology mitigates the effect of scaling on signal delay and cross-talk in local and intermediate interconnects. However, the benefits of new materials may not be sufficient for scaling long global interconnects due to the increasing RC delays. The near term solution adopted by the semiconductor industry to minimize the relative delay, according to the 1TRS roadmap, has been to increase the aspect ratio of interconnects. However, the increase in metal thickness, reduction in metal pitch and continuing voltage scaling with each technology generation will progressively exacerbate the noise problem due to interconnect capacitive and inductive coupling effects and will eventually become the dominant problem over local and global propagation delays.The research described in this proposal will address the signal propagation delay and cross-talk noise limitations in deep submicron interconnects by introducing a fundamental change in the signaling approach: the use of current-mode band-limited signaling to reduce the signal delay and cross-talk noise bottlenecks in CMOS VLSI's. To reduce cross-talk noise due to capacitive and inductive effects, the proposed signaling scheme based on band-limited basis waveforms will partially replace the square pulses in critical communication links within the system. A preliminary remit from the proposed band-limited signaling scheme in 0.35-urn CMOS process shows capacitive cross-talk noise reduction beyond 30 percent for aluminum and copper interconnects. An attractive result from the proposed signaling approach is that given the signal bandwidth and noise margin requirements, longer interconnects lines or higher interconnect densities can be achieved.To overcome the bandwidth limitations in the deep submicron regime, new approaches to high-speed signaling are required. In the proposed research, we intend to use current-mode circuit techniques to improve the bandwidth performance and reduce signal delay. Current-mode sensing has received limited attention for signaling in global interconnections partially due to the popularity of voltage-mode full swing repeater insertion methodologies. . It can be shown that as CMOS technology continues to scale, the number of repeaters required to achieve the projected performance criteria will increase dramatically and constitute a significant portion of the total system power dissipation. Therefore, current-mode sensing circuits will increasingly become popular in this deep submicron IC era.Accurate estimation of propagation delay and cross-talk noise in long global interconnects plays an important role in the early design stages of high performance VLSI systems. Various techniques based on simulations and/or analytical closed-form formulations have been proposed to model delay and cross-talk in interconnects. The bulk of the work dedicated to this area targets capacitively terminated lines for voltage mode signaling. However, with the increasing speed requirements in VLSI circuits, current mode signal transporting techniques may provide an attractive solution to some of the challenges caused by aggressive interconnect scaling. To accommodate current-mode signaling techniques, we propose to derive efficient closed-form analytical models for a driven distributed RC line with arbitrary termination. The accuracy of this work is predicted to be the same as Elmore Delay formulation, extended to accommodate current-mode type circuits.In this research, we intend to develop the theoretical basis for the proposed current-mode band-limited signaling scheme and analytically formulate its impact on cross-talk noise and signal delay reduction. We will target our study toward understanding its effects on interconnect coupling noise. Study of circuit design issues will be followed by prototype fabrication for conceptual and experimental verification. Finally, we intend to apply this knowledge to build a high performance wide bus system to prove the noise reduction advantages.

由于信号延迟和串扰噪声的增加，最近亚微米级CMOS规模的趋势表明，全球互连将日益成为主要的性能限制。铜线和低k布线技术的实施减轻了局部和中间互连中的信号延迟和串扰的比例影响。然而，由于RC延迟的增加，新材料的好处可能不足以扩展长的全球互连。根据1TRS路线图，半导体行业为将相对延迟降至最低而采取的近期解决方案是增加互连的纵横比。然而，随着每一代工艺的产生，金属厚度的增加、金属间距的减小和电压的持续缩放将逐渐加剧由互连的电容和电感耦合效应引起的噪声问题，并最终成为局部和全局传播延迟的主要问题。在该建议中描述的研究将通过在信号方法中引入根本的改变来解决深亚微米互连中的信号传播延迟和串扰噪声限制：使用电流模式带限信号来减少CMOSVLSI中的信号延迟和串扰噪声瓶颈。为了减少由于电容和电感效应而产生的串扰噪声，所提出的基于带限基本波形的信令方案将部分取代系统内关键通信链路中的方脉冲。建议的限带信号方案在0.35-urn CMOS工艺中的初步结果显示，对于铝和铜互连，电容式串扰噪声降低了30%以上。提出的信令方法的一个吸引人的结果是，在给定信号带宽和噪声容限的情况下，可以实现更长的互连线或更高的互连密度。为了克服深亚微米区域的带宽限制，需要新的高速信令方法。在提出的研究中，我们打算使用电流模式电路技术来提高带宽性能和降低信号延迟。由于电压型全摆幅中继器插入方法的普及，电流模式检测在全球互连中的信令方面受到的关注有限。。可以看出，随着CMOS工艺的不断扩展，达到预期性能标准所需的中继器数量将急剧增加，并在整个系统功耗中占据相当大的比例。因此，在这个深亚微米的集成电路时代，电流模式检测电路将变得越来越流行。准确估计长全局互连中的传播延迟和串扰噪声在高性能VLSI系统的早期设计阶段具有重要作用。已经提出了基于模拟和/或解析封闭形式公式的各种技术来对互连中的延迟和串扰进行建模。致力于这一领域的大部分工作针对的是用于电压模式信号的电容端接线路。然而，随着VLSI电路对速度的要求越来越高，电流模式信号传输技术可能会为积极的互连扩展带来的一些挑战提供一个有吸引力的解决方案。为了适应电流模式信令技术，我们建议为任意端接的驱动分布式RC线路推导有效的闭合形式的分析模型。这项工作的精度预计与Elmore延迟公式相同，扩展到适用于电流模式类型的电路。在本研究中，我们打算为所提出的电流模式带限信号方案建立理论基础，并解析地描述其对串扰噪声和信号延迟的影响。我们的研究目标是了解其对互连耦合噪声的影响。在研究电路设计问题之后，将进行原型制造，以进行概念和实验验证。最后，我们打算将这些知识应用于构建一个高性能的宽母线系统，以证明降噪的优势。