Design of Giga-Scale CMOS Communications Systems: An Integrated Approach

研究目标是开发千兆级CMOS系统的设计方法。重点是高比特率数字通信。该方法超越了VLSI设计方法的算法，架构，逻辑，电路和技术方面的界限。这项研究分为两部分。首先是对千兆级计算中功率区域速度和可靠性的基本限制的研究。活动包括：(a)为任何给定算法和实现技术建立功耗、面积、速度和可靠性的非经验和可实现的界限，以及(b)探索实现这些基本界限的方法。在第二部分，算法，架构和系统设计的高比特率通信系统进行了研究。活动包括：(a)为高比特率数字通信和信号处理应用开发功率、面积和速度最佳的VLSI算法和架构；(b)建立通信和信号处理应用程序；(b)为ATM和IMTV以及无线扩频系统构建155.52 Mb/s双绞线传输的实用系统。

The research objective is to develop methodologies for the design of giga-scale CMOS systems. A focus is high bit rate digital communications. The approach transcends boundaries between algorithmic, architectural, logic, circuit and technological aspects of the VLSI design methodology. The research has two parts. The first is an investigation of fundamental limits on power area speed and reliability in giga-scale computation. Activities include: (a) establishing non-empirical and achievable bounds on the power dissipation, area, speed and reliability for any given algorithm and implementation technology' and (b) exploring methods to achieve these fundamental bounds. In the second part, algorithms, architectures, and systems for design of high-bit rate communications systems are being investigated. Activities include: (a) developing power, area, and speed-optimal VLSI algorithms and architectures for high-bit rate digital communications and signal processing applications; and (b) building communications and signal processing applications; and (b) building practical systems for 155.52 Mb/s transmission over twisted-pair wiring for ATM and IMTV, and wireless spread-spectrum systems.