Design of Giga-Scale CMOS Communications Systems: An Integrated Approach

千兆级 CMOS 通信系统的设计：一种集成方法

• 批准号: 9623737
• 负责人: Naresh Shanbhag
• 金额: $ 22万
• 依托单位: University of Illinois at Urbana-Champaign
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1996
• 资助国家: 美国
• 起止时间: 1996-06-01 至 2001-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9623737&HistoricalAwards=false
• 关键词: Design; Giga; Scale; CMOS; Communications

The research objective is to develop methodologies for the design of giga-scale CMOS systems. A focus is high bit rate digital communications. The approach transcends boundaries between algorithmic, architectural, logic, circuit and technological aspects of the VLSI design methodology. The research has two parts. The first is an investigation of fundamental limits on power area speed and reliability in giga-scale computation. Activities include: (a) establishing non-empirical and achievable bounds on the power dissipation, area, speed and reliability for any given algorithm and implementation technology' and (b) exploring methods to achieve these fundamental bounds. In the second part, algorithms, architectures, and systems for design of high-bit rate communications systems are being investigated. Activities include: (a) developing power, area, and speed-optimal VLSI algorithms and architectures for high-bit rate digital communications and signal processing applications; and (b) building communications and signal processing applications; and (b) building practical systems for 155.52 Mb/s transmission over twisted-pair wiring for ATM and IMTV, and wireless spread-spectrum systems.

本研究的目标是发展千兆级CMOS系统的设计方法。 重点是高比特率数字通信。 该方法超越了VLSI设计方法的算法、架构、逻辑、电路和技术方面之间的界限。 本研究分为两部分。 第一个是在千兆级计算的功率区的速度和可靠性的基本限制的调查。 活动包括：（a）为任何给定算法和实现技术建立关于功耗、面积、速度和可靠性的非经验的和可实现的界限，以及（B）探索实现这些基本界限的方法。 在第二部分中，高比特率通信系统的设计算法，架构和系统正在进行研究。 活动包括：（a）开发用于高比特率数字通信和信号处理应用的功率、面积和速度最优的VLSI算法和结构;（B）建立通信和信号处理应用;（B）建立用于ATM和IMTV的双绞线上的155.52 MB/s传输的实用系统，以及无线扩频系统。