PDS: A Flexible Architecture for Executing Component Software at 100 Teraops
PDS: A Flexible Architecture for Executing Component Software at 100 Teraops
批准号:
9634947
负责人:
Andrew Chien
金额:
$10.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
1996
资助国家:
美国
项目状态:
已结题
起止时间:
1996-08-15 至 1998-07-31
中文摘要
100TeraOps机器的应用软件将基于组件软件(库、图形用户界面、问题解决环境)和互操作性框架(CORBA、OLE、SOM等)的广泛使用,产生的应用程序是各种程序的复杂集合体。为了支持这些应用,机器必须提供可编程接口(即高效的共享地址空间和数据移动)和可扩展的高性能。这个项目将研究一种灵活的机器体系结构,它认识到这些技术现实,不仅支持先进的软件结构,而且利用它们来配置其可编程硬件,使其自身适应应用。编程的灵活性可以提供广泛的方便接口,从统一的高速缓存一致的共享内存,到较小的共享内存系统的集群,再到完全分布式内存。除了一系列接口外,这台灵活的机器还可以定制操作和协议,利用适当的机制和策略将系统所有级别的关键性能方面--通信--降至最低。这种机器设计利用了对最佳架构机制、可定制高速缓存一致性以及过程间分析、可编程硬件和硬件合成技术方面的技术进步的丰富研究,以实现通用的高性能。
英文摘要
Application software for 100 TeraOps machines be based on the increasing use of component software (libraries, GUIs, problem solving environments) and extensive use of interoperability frameworks (CORBA, OLE, SOM, etc.), producing applications which are complex conglomerates of variegated programs. To support these applications, the machine must present a programmable interface (i.e. efficient shared address spaces and data movement) and scaleable high performance. This project will study a flexible machine architecture that recognizes these technological realities and not only supports advanced software structures, but exploits them to configure its programmable hardware, adapting itself to the application. The programming flexibility can provide a wide range of convenient interfaces, ranging from uniform cache-coherent shared memory, to clusters of smaller shared memory systems, to fully distributed memory. In addition to a range of interfaces, this flexible machine can customize both operations and protocols, exploiting appropriate mechanisms and policies to minimize the critical performance aspect--communication--at all levels of the system. This machine design leverages the wealth of research into optimal architectural mechanisms, customizable cache-coherence, as well as technological advances in interprocedural analysis, programmable hardware, and hardware synthesis technology, to achieve general-purpose high performance.
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