CAREER: Integrating Architecture-Level Simulation with Industrial CAD Tools for Prototyping High-Performance Coprocessors

职业：将架构级仿真与工业 CAD 工具集成以制作高性能协处理器原型

• 批准号: 9702483
• 负责人: Martin Herbordt
• 金额: $ 21.88万
• 依托单位: University of Houston
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1997
• 资助国家: 美国
• 起止时间: 1997-09-01 至 2002-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9702483&HistoricalAwards=false
• 关键词: CAREER; Integrating; Architecture; Level; Simulation

This research involves the creation of a co-processor architecture evaluation environment which integrates architecture-level simulation with industrial CAD tools. The end-goal is to facilitate the design of high-performance domain-specific co-processors. In the evaluation environment, the designer will have the capability of 'test driving' a wide variety of design alternatives with respect to real application ppograms. The mechanism is to `drop-in' components into predetermined templates, gauge their effect on virtual machine instruction execution, and use that information to evaluate virtual machine instruction traces. There are three aspects to this research: (i) integrating existing or user-constructed component libraries and synthesis tools into an architecture- level model generator, (ii) integrating the same into an interprocessor network simulator, and (iii) extending an existing architecture-level simulator to include data parallel SPMD architectures. A graphic user interface is being developed to help the user mix-and-match components. The resulting environment will target not only professional designers, but also students in computer and advanced digital design classes.

这项研究涉及创建协作处理器架构评估环境，该评估环境将体系结构级别的模拟与工业CAD工具集成在一起。最终目标是促进高性能域特异性协作过程的设计。在评估环境中，设计人员将具有“测试驱动”的能力，相对于实际应用程序图图。该机制是将组件“插入”到预定的模板中，衡量其对虚拟机指令执行的影响，并使用该信息来评估虚拟机指令轨迹。这项研究有三个方面：（i）将现有或用户构建的组件库和合成工具集成到体系结构级别模型生成器中，（ii）将相同集成到Internecorser网络模拟器中，（iii）扩展现有的架构级别级别模拟器以包括数据并行SPMD Architecters。正在开发图形用户界面，以帮助用户混合组件。最终的环境不仅针对专业设计师，还针对计算机和高级数字设计课程的学生。