CAREER: Integrating Architecture-Level Simulation with Industrial CAD Tools for Prototyping High-Performance Coprocessors

这项研究涉及创建一个协处理器架构评估环境，集成了架构级仿真与工业CAD工具。最终目标是促进高性能领域特定的协处理器的设计。在评估环境中，设计人员将有能力“测试驾驶”各种各样的设计方案相对于真实的应用程序。该机制是将组件“放入”预定的模板中，测量它们对虚拟机指令执行的影响，并使用该信息来评估虚拟机指令跟踪。这项研究有三个方面：（i）将现有的或用户构建的组件库和合成工具集成到架构级模型生成器中，（ii）将其集成到处理器间网络模拟器中，以及（iii）扩展现有的架构级模拟器以包括数据并行SPMD架构。正在开发一个图形用户界面，以帮助用户混合和匹配组件。由此产生的环境将不仅针对专业设计师，也包括计算机和高级数字设计课程的学生。

This research involves the creation of a co-processor architecture evaluation environment which integrates architecture-level simulation with industrial CAD tools. The end-goal is to facilitate the design of high-performance domain-specific co-processors. In the evaluation environment, the designer will have the capability of 'test driving' a wide variety of design alternatives with respect to real application ppograms. The mechanism is to `drop-in' components into predetermined templates, gauge their effect on virtual machine instruction execution, and use that information to evaluate virtual machine instruction traces. There are three aspects to this research: (i) integrating existing or user-constructed component libraries and synthesis tools into an architecture- level model generator, (ii) integrating the same into an interprocessor network simulator, and (iii) extending an existing architecture-level simulator to include data parallel SPMD architectures. A graphic user interface is being developed to help the user mix-and-match components. The resulting environment will target not only professional designers, but also students in computer and advanced digital design classes.