Data Layout Optimizations for High-Performance Architectures

编译技术通过允许用户实现高程序性能而无需过度担心底层硬件架构的细节，为计算科学的成功做出了贡献。大多数编译器优化都集中在提高计算效率上，但处理器和内存速度之间的差距越来越大，这使得利用寄存器和缓存的重用也变得非常重要。这个项目将探索通过修改程序中的数据布局来提高程序性能的技术，以提高空间局部性，并避免冲突未命中和错误共享等不良内存影响。 目标优化包括修改变量的基址、更改结构内的字段偏移量、相关数据的分组和转置、填充、转置和重新索引数组维度。 该项目的主要目标是开发用于指导数据布局优化的算法，无论是单独的还是作为包括计算转换的整体优化策略的一部分。 为了评估对科学应用的影响，优化将在斯坦福大学SUIF编译器中实现，并在标量和并行架构的Perfect、NAS和SPEC等基准套件上进行测试。

Compilation technology has contributed to the success of computational science by allowing users to achieve high program performance without worrying excessively about details of the underlying hardware architecture. Most compiler optimizations focus on improving computation efficiency, but the growing disparity between processor and memory speeds has made exploiting reuse of registers and cache important as well. This project will explore techniques for improving program performance by modifying the data layout in a program to improving spatial locality and avoid adverse memory effects such as conflict misses and false sharing. Target optimizations include modifying the base addresses of variables, changing fields offsets within structures, group-and-transpose of related data, padding, transposing, and reindexing array dimensions. The main goal of this project is to develop heuristics for guiding data layout optimizations, both individually and as part of an overall optimization strategy which includes computation transformations. To evaluate the impact on scientific applications, optimizations will be implemented as passes in the Stanford SUIF compiler and tested on benchmark suites such as Perfect, NAS, and SPEC for both scalar and parallel architectures.